用于SCA ASIC测试的数字读出模块设计

高速开关电容阵列(SCA)具有高速采样、低功耗的特点,基于SCA的高速波形数字化是目前高精度时间测量的一个重要研究方向。为此,我们开展SCA芯片的研究,目前已设计完成原型ASIC设计,并正在进行后续版本的改进设计。为便于未来多版本ASIC的测试和评估,需设计具有一定通用性的数字读出模块,本论文工作主要介绍此模块的设计工作以及相应的数据读出软件。数字读出模块基于FPGA实现对待测ASIC的控制、配置及数据读出,采用DDR3片外存储芯片,使用USB3.0等接口进行数据传输;上位机软件基于Python3.7设计,实现了数据采集与波形绘制等功能。目前已使用设计完成的数字读出模块对第2版SCA ASIC进行了初步的测试,测试结果表明,此读出模块工作正常,且SCA芯片输出结果符合预期。     

兰州反应显微成像谱仪实验中多路定标器的设计

介绍了一种基于PXI总线的高精度、多通道定标器。可测量脉冲信号的最高重复频率为100 MHz,最高计数可达240。定标器有2种工作模式:定时计数模式和精确触发测量模式。定时计数模式工作在低计数率下(s 1 MHz);精确触发测量模式可以工作在高计数率下(~ 100 MHz),可以满足兰州反应显微成像谱仪实验中对定标器的要求。基于可编程逻辑器件FPGA进行设计,使之变得灵活,方便进行升级和改造。This article introduces a high resolution and multi-channel scaler based on PXI-3U standard. The maximum repetition frequency of the input signal is 100 MHz, with a counting scale up to 240. This scaler is able to operate in two working modes: counting within a certain time period or between two adjacent input trigger signals. The rst mode is designed for a low counting rate (~ 1 MHz), while the second mode for a high rate ( 100 MHz). Test results indicate that this scaler has a good performance, beyond the application requirement in the experiment of the reaction microscope at Lanzhou (ReMiLa). Besides, with the application of Field Programmable Gate Array (FPGA), this scaler module is exible and convenient to be upgrade in future.     

反相高效液相色谱法测定叶酸及其相关物质

建立了反相高效液相色谱法对叶酸及其相关物质的分离测定方法。对叶酸原料药进行了测定,色谱柱为JASCO C18柱(250mm×4.6mmi.d.,5μm),流动相为V(0.05mol LKH2PO4):V(0.1mol LKOH)∶V(甲醇)=78∶2∶20,流速为1.0mL min,柱温为30℃。叶酸检出限为1.0ng,叶酸的质量分数为98.52%～99 87%;加标回收率为95.22%～100.83%。该法快速简捷,精密度高,重现性好,可用于叶酸的质量控制。     

Prototype of time digitizing system for BESⅢ endcap TOF upgrade

The prototype of a time digitizing system for the BESⅢ endcap TOF (ETOF) upgrade is introduced in this paper. The ETOF readout electronics has a distributed architecture. Hit signals from the multi-gap resistive plate chamber (MRPC) are signaled as LVDS by front-end electronics (FEE) and are then sent to the back-end time digitizing system via long shield differential twisted pair cables. The ETOF digitizing system consists of two VME crates, each of which contains modules for time digitization, clock, trigger, fast control, etc. The time digitizing module (TDIG) of this prototype can support up to 72 electrical channels for hit information measurement. The fast control (FCTL) module can operate in barrel or endcap mode. The barrel FCTL fans out fast control signals from the trigger system to the endcap FCTLs, merges data from the endcaps and then transfers to the trigger system. Without modifying the barrel TOF (BTOF) structure, this time digitizing architecture benefits from improved ETOF performance without degrading the BTOF performance. Lab experiments show that the time resolution of this digitizing system can be lower than 20 ps, and the data throughput to the DAQ can be about 92 Mbps. Beam experiments show that the total time resolution can be lower than 45 ps.     

Study of linearity for a high dynamic range calorimeter

A high dynamic range calorimeter has been designed for the DArk Matter Particles Explore(DAMPE) satellite. It consists of 308 BGO crystals, multi-dynode readout PMTs and front end electronics system. We have built on previous research to show that BGO fluorescence should not be saturated by high electron energy density under DAMPE's energy range. A BGO fluorescence simulator is set up to calibrate the energy range of the dynodes, while a cosmic-ray unit is used to calibrate 1 MIP with the ADC count in dynode 8. Linearity is achieved for the dynamic range from 0.5 MIPs to 1.26×105MIPs. The requirements of DAMPE can thus be satisfied.     

硅锆复合包覆BiVO4晶体的表征及其机理研究

利用正硅酸乙酯(TEOS)和氧氯化锆(ZrOCl2·8H2O)的水解反应并经高温煅烧后,在BiVO4晶体表面形成SiO2·ZrSiO4膜,以提高BiVO4的耐高温性.采用红外光谱仪、X射线衍射仪、差热分析仪对产品进行了表征,并得出结论:包覆SiO2·ZrSiO4膜后的BiVO4晶体,其耐热温度由680℃提高到1000℃,并对包覆机理进行了探讨.     

Time calibration for the end cap TOF system of BESⅢ

The time calibration for end cap TOF system of BESⅢ is studied in this paper. It has achieved about 110 ps time resolution for muons in dimu events. The pulse height correction using electronic scan curve and the predicted time calculated using Kalman filter method are introduced. This paper also describes the study of using electrons and muons as calibration samples.     

高重频束流采集处理器原型样机的设计

为了实现对高重频硬X射线自由电子激光装置(SHINE)条带型BPM(Beam Position Monitor)系统信号的数字化采样和处理,研制了高重频束流采集处理器原型样机。处理器拥有四通道输入,最高达1 GSps的采样率,16 bit采样位数,采用XILINX公司带有嵌入式CPU(Central Processing Unit)的ZYNQ系列FPGA(Field Programmable Gate Array),可以运行Linux系统,同时可以实现高速采样数据的缓存与读出。处理器采用子母板结构设计,子板为ADC(Analog To Digital Converter)采样板,母板为FPGA数字处理板,子母板通过FMC(FPGA Mezzanine Card)接口进行数据传输。ADC采用JESD204B协议进行数据传输,子母板间通过16对差分信号连接通道,最大总传输速率达到80 Gbps。ADC采样数据传入数字母板后,经过FIFO和DDR的缓存,最后通过TCP/IP协议由RJ45接口传输到上位机进行处理和分析,RJ45接口的数据传输速率约为900 Mbps。经过测试,ADC采集子板的带宽高于480 MHz,且在480 MHz带宽内有效位高于10位。FPGA数字母板运行经Petalinux编译的Linux系统,可以实现对连续或者触发模式下,四通道一百万个采样点的存储与数据传输。整个设计可以满足设计要求。     

基于SCA ASIC的高精度时间测量原型电子学设计

基于高速波形数字化实现高精度时间测量是核与粒子物理实验读出电子学中的研究热点。本工作针对高精度时间测量的需求基于实验室自主研发的开关电容阵列(Switched Capacitor Array, SCA)专用集成电路(Application Specific Integrated Circuit,ASIC)开展16通道集成的时间测量电子学原型的设计,输入信号经过SCA采样和量化后传输至现场可编程逻辑阵列(Field Programmable Gate Array, FPGA),在FPGA中进行误差修正、时间内插和数字甄别提取出时间信息。目前已在实验室环境下完成此电子学的时间精度测试,测试结果表明,此电子学可以实现好于10 ps RMS(Root Mean Square)的时间精度。