用于SCA ASIC测试的数字读出模块设计

高速开关电容阵列(SCA)具有高速采样、低功耗的特点,基于SCA的高速波形数字化是目前高精度时间测量的一个重要研究方向。为此,我们开展SCA芯片的研究,目前已设计完成原型ASIC设计,并正在进行后续版本的改进设计。为便于未来多版本ASIC的测试和评估,需设计具有一定通用性的数字读出模块,本论文工作主要介绍此模块的设计工作以及相应的数据读出软件。数字读出模块基于FPGA实现对待测ASIC的控制、配置及数据读出,采用DDR3片外存储芯片,使用USB3.0等接口进行数据传输;上位机软件基于Python3.7设计,实现了数据采集与波形绘制等功能。目前已使用设计完成的数字读出模块对第2版SCA ASIC进行了初步的测试,测试结果表明,此读出模块工作正常,且SCA芯片输出结果符合预期。

Design of a Digital Readout Module for SCA ASIC Testing

Switched Capacitor Array (SCA) features high-speed sampling and low power consumption. High-speed waveform digitization based on SCA is an important research direction for high-precision time measurement. We are designing the SCA ASIC chips, of which several prototypes have been designed and the improvements are ongoing. In order to test and evaluate the future SCA ASIC chips, it is necessary to design a digital readout module with good compatibility. This paper presents the design of the readout module and the data readout software. The digital readout module integrates the functionality of the control, configuration and data readout of the ASIC under test within one FPGA device. A DDR3 chip is used for data caching, and a USB3.0 interface is designed for data transmission. The readout software is designed based on Python3.7 and contains the functions such as data acquisition and waveform drawing. This module was successfully used in the initial testing of the second version of the SCA prototype ASIC, and the test results indicate that the readout module works as expected.