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基于高速波形数字化实现高精度时间测量是核与粒子物理实验读出电子学中的研究热点。本工作针对高精度时间测量的需求基于实验室自主研发的开关电容阵列(Switched Capacitor Array, SCA)专用集成电路(Application Specific Integrated Circuit,ASIC)开展16通道集成的时间测量电子学原型的设计,输入信号经过SCA采样和量化后传输至现场可编程逻辑阵列(Field Programmable Gate Array, FPGA),在FPGA中进行误差修正、时间内插和数字甄别提取出时间信息。目前已在实验室环境下完成此电子学的时间精度测试,测试结果表明,此电子学可以实现好于10 ps RMS(Root Mean Square)的时间精度。 相似文献
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LHAASO(Large High Altitude Air Shower Observatory)WCDA(Water Cerenkov Detector Array)要求其读出电子学实现大动态范围下精确的时间和电荷测量,为此设计了一款前端读出芯片PASC(Pre-Amplifier and Shaping Circuit) ASIC(Application Specific Integrated Circuit),即将用于LHAASO WCDA第三水池的读出。为了满足对此芯片大批量测试需求,设计了此ASIC测试系统,实现了对芯片时间和电荷性能的自动化测试。在介绍此芯片基本工作原理的基础上,讨论了测试系统的设计方案和基本结构,包括硬件电路设计和自动化测试软件设计。该测试系统已应用于LHAASO工程项目的芯片筛选并且已完成了100片芯片的测试工作,能够通过中央控制软件,与多台仪器通讯,进行仪器控制,完成自动化测试和数据记录。这一自动化测试方法,更适用于大动态范围下、高精度读出芯片的性能测试和评估,大大简化测试流程,尤其能够大幅提升批量测试中大量重复性测试步骤的工作效率。文中展示了基于此测试系统已完成的100片芯片的测试结果,结果表明,芯片各项性能参数满足LHAASO第三水池工程应用需求。 相似文献
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基于开关电容阵列(SCA)技术可以实现超高速的波形数字化。本研究是基于实验室设计完成的FEL_SCA芯片进行8通道2 Gsps的波形数字化模块的设计,电路的配置和读出控制功能集成在单个FPGA中完成,此外该模块还包含SDRAM缓存及USB接口。目前已在实验室环境下对其进行了直流电压测试、瞬态波形测试和带宽测试,测试结果表明,在FEL_SCA芯片的输入动态范围100 mV~1 V之间,本波形数字化模块的INL好于1%,通道的RMS噪声约为1.76 mV,带宽约为450 MHz,达到设计目标。Switched Capacitor Arrays (SCAs) can be employed to achieve high speed waveform digitization. In this paper, we designed an 8-channel 2 Gsps waveform digitization module using four SCA chips named FEL_SCA which was designed in our laboratory. In this module, we used a FPGA device for data readout and circuit configuration. Besides, a 128 Mb SDRAM and USB interface were integrated in this module. We have also conducted DC voltage tests, transient tests and bandwidth tests on this module. The results indicate that in the signal voltage range 100 mV~1 V, the INL is better than 1%, the RMS noise is about 1.76 mV and the -3 dB input bandwidth is 450 MHz. 相似文献
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《物理学报》2021,(17)
硅像素探测器因具有优异的空间分辨率、极高的耐计数能力和较低的功耗等优点,近年来已被广泛应用于高能对撞机实验的顶点探测器和内径迹探测器.基于MIMOSA28芯片的硅像素探测器研究是北京谱仪Ⅲ漂移室内室的升级预研方案之一,该方案计划建造一个漂移室内室1/10规模的模型.探测模块是该模型的基本探测单元.为了对探测模块的性能进行研究,搭建了实验室测试系统.该系统主要由五层探测模块、读出电子学系统以及数据获取系统组成.本文围绕带有触发标记的连续数据读出方法的实现、探测模块的噪声水平和放射源响应测试以及击中位置重建算法研究展开.测试结果验证了探测模块工作性能良好,触发读出逻辑正确,而且重建算法准确有效,为后续探测模块性能的进一步研究奠定了基础. 相似文献
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Back-n是中国散裂中子源(CSNS)的反角中子束线,适用于精密核数据的测量。该装置的谱仪读出电子学采用共性化设计方法,利用高速波形数字化技术精密采集探测器输出信号波形。为完成对两通道、1 GSps,12 bit采样数据的读出和板载外设的控制,可以使用一种基于FPGA的高速数据实时读出方法。该方法不仅实现了数据接收、缓存上传等通用需求,还通过软件配置满足了实时触发处理等针对特定物理实验的特性需求。此外,FPGA的灵活使通过固件更新支持新实验或添加新功能成为可能。测试结果表明,该方法能够适应Back-n波形数字化模块高速数据读出的需求,峰值处理能力可达24 Gbps,符合物理实验需求。目前,基于实时读出方法实现的波形数字化模块已完成中子源谱仪实验现场的安装,工作稳定。Back-n is a back-streaming beam line at China Spallation Neutron Source, which is suitable for measure nuclear data precisely. The readout electronics of the spectrometers at this facility adopts general-propose design method, using high-speed waveform digitizing technology to record the detector output signal accurately. To read out two channels, 1 GSps, 12 bit sample data and control on-board devices, the real-time readout method of high-speed data based on FPGA technology can be considered. The method not only realizes the general requirements of the data upload, but also processes real-time triggers according to experiments via configuration. In addition, due to the flexibility of FPGAs, new experiments or new features can be supported through firmware updates. The test results show that the method is suitable for the high-speed data readout of field digitizing module at Back-n and peak capacity reaches up to 24 Gbps, which meets the requirements of the physical experiment. The field digitizing modules based on this method were installed at Back-n and work normally. 相似文献
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介绍了激光陀螺(RLG)读出信号高速采集系统的设计和实现方案。该系统包括板卡和相应的应用软件,提供两路最高60MHz采样频率、14位精度的数据采集通道,能够同时对RLG两路光强拍频信号进行高速高精度数据采集,为RLG特性分析提供重要依据。该系统通过上位机软件控制板卡的工作状态、设置和切换采样模式。板卡利用FPGA接收计算机指令并协调控制模数转换器、SDRAM和USB接口芯片,完成RLG输出拍频信号的采集、缓存和传输。FP—GA设计中结合了硬件逻辑高速灵活的优点和NIOSⅡ软核处理器在控制方面的优势。SDRAM完成海量数据缓存,USB接口芯片工作在SlaveFIFO模式下,实现板卡与计算机的通信。实验证明该系统工作稳定,在RLG测试和性能分析中具有很好的实用性。 相似文献
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高速高精度模数转换器(ADC)广泛应用于信号处理领域,其动态性能直接决定系统性能的优劣。由于实际使用的芯片与设计的额定指标间会存在偏差,有必要评估ADC的实际动态性能。基于FPGA及Labview实现了一个低成本、高可靠性的高速高精度ADC性能评估系统。系统由底层控制待评估ADC子卡,提供精确的采样样本;采用异步FIFO进行数据缓存, DMA方式优化数据存储;Labview定义通信模块,结合Matlab测试脚本完成动态参数测试。最后使用ADI公司的AD9467进行了测试验证。实验结果表明,该系统运行稳定,与datasheet相比,参数误差不超过1.89%,达到了IEEE Std 1241-2000的测试标准,降低了测试系统构建难度和成本。 相似文献
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任意波形发生器作为测试测量设备的一种重要仪器,在航空航天的测量与控制技术领域中得到了广泛应用。当前市场成熟任意波形发生器产品多为国外产品或者国内厂商基于国外FPGA和DAC研制的产品。为了打破技术垄断,提高国产任意波形发生器的自主技术保障能力,研制基于国产芯片的任意波形发生器愈发重要。随着国产芯片设计技术提升,国产FPGA和DAC的性能显著提高,并得到了广泛应用。PXI总线作为当前仪器领域的主要总线类型之一,可以满足大部分测试仪器的通讯要求。基于国产FPGA和DAC器件,从硬件设计和软件设计两个方面出发,成功研制了一款采样率为100MSa/s的 PXI总线任意波形发生器模块,实现了43MHz信号输出,通过实验测试了模块的功能和性能,完全满足模块指标要求,充分证明了国产芯片在工程设计中的性能特性。 相似文献
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《中国物理C(英文版)》2016,(8)
A scalable readout system(SRS) is designed to provide a general solution for different micro-pattern gas detectors in various applications.The system mainly consists of three kinds of modules:the ASIC card,the adapter card and the front-end card(FEC).The ASIC cards,mounted with particular ASIC chips,are designed for receiving detector signals.The adapter card is in charge of digitizing the output signals from several ASIC cards.The PEC,edged-mounted with the adapter,has field-programmable gate array(FPGA)-based reconfigurable logic and I/O interfaces,allowing users to choose different ASIC cards and adapters for different experiments,which expands the system to various applications.The FEC transfers data through Gigabit Ethernet protocol realized by a TCP processor(SiTCP) IP core in FPGA.By assembling a flexible number of FECs in parallel through Gigabit Ethernet,the readout system can be tailored to specific sizes to adapt to the experiment scales and readout requirements.In this paper,two kinds of multi-channel ASIC chip,VA140 and AGET,are applied to verify the scalability of this SRS architecture.Based on this VA140 or AGET SRS,one FEC covers 8 ASIC(VA140) cards handling 512 detector channels,or 4 ASIC(AGET) cards handling 256 detector channels,respectively.More FECs can be assembled in crates to handle thousands of detector channels. 相似文献
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SCAs(Switched Capacitor Arrays) have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents( 4m A max) and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 m W/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 m V with 625 k Hz full-scale sine wave as input, sampling at 40 MSPS(Mega-samples per Second) and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 m V. The test results validate the feasibility of the MOS capacitor. 相似文献
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介绍了兰州重离子加速器冷却储存环(HIRFL-CSR)外靶实验中时间起点探测器(T0)的前端电子学原型模块的设计与测试。探索了基于过阈时间法和专用集成电路NINO芯片进行多气隙电阻板室探测器信号读出的模拟前端电路的设计技术,并实际完成了原型电子学模块的设计。此模块共集成6个测量通道,可以进行前沿甄别及电荷时间变换。目前已经在实验室条件下完成了各项电子学性能测试,包括不同甄别阈值下的时间精度测试以及不同输入信号幅度下的输出脉宽测试。测试结果表明,在100 fC至2 pC的动态范围内,此模块时间精度好于20 ps,满足应用需求,这也为进一步的电子学系统设计做好了准备。A prototype front end electronics (FEE) module is designed for the T0 detector in the External Experiment in CSR (Cooling Storage Ring) of HIRFL (Heavy Ion Research Facility in Lanzhou). Based on the Time-Over-Threshold method and NINO ASIC, a total of 6 channels are integrated in the module, and both high precision leading edge discrimination and Charge-to-Time Conversion can be achieved, which satisfies the readout requirement of MRPC (Multi-gap Resistive Plate Chamber). A series of tests were also conducted in the laboratory, including time precision tests with different thresholds and output pulse width tests with different input signal amplitudes. Test results indicate that this prototype module functions well, and the time precision is better than 20 ps in the dynamic range from 100 fC to 2 pC, which is beyond application requirement. Through this work, preparation is made for the future readout system design. 相似文献
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针对北京正负电子对撞机改造工程(BEPC II)直线加速器束流位置测量电子学系统故障率上升这一现状,结合BEPC II直线加速器束流参数以及BPM电子学ADC芯片带通采样的需求,设计了隔离度高、幅相一致性好的数字BPM射频前端电子学模块。数字BPM电子学系统采用MicroTCA 4.0系统架构,以FPGA作为主控制器,基于EDA软件开发设计。重点介绍了射频前端电子学模块中射频功率放大器、数字可调衰减器、带通滤波器等设计和实验室及在线测试结果。BEPC II对撞模式下,使用正电子束流,完成电子学系统在线测试,x方向位置测量精度约为38.46 μm,y方向位置测量精度约为26.16 μm,其测量精度和系统稳定性优于商用模拟BPM电子学模块,能够满足BEPC II直线加速器束流位置测量需求。 相似文献