Study on the negative bias temperature instability effect under dynamic stress

This paper studies negative bias temperature instability (NBTI) under alternant and alternating current (AC) stress.Under alternant stress,the degradation smaller than that of single negative stress is obtained.The smaller degradation is resulted from the recovery of positive stress.There are two reasons for the recovery.One is the passivation of H dangling bonds,and another is the detrapping of charges trapped in the oxide.Under different frequencies of AC stress,the parameters all show regular degradation,and also smaller than that of the direct current stress.The higher the frequency is,the smaller the degradation becomes.As the negative stress time is too small under higher frequency,the deeper defects are hard to be filled in.Therefore,the detrapping of oxide charges is easy to occur under positive bias and the degradation is smaller with higher frequency.     

SILC during NBTI Stress in PMOSFETs with Ultra-Thin SiON Gate Dielectrics

Negative bias temperature instability （NBTI） and stress-induced leakage current （SILC） both are more serious due to the aggressive scaling lowering of devices. We investigate the SILC during NBTI stress in PMOSFETs with ultra-thin gate dielectrics. The SILC sensed range from -1 V to 1 V is divided into four parts： the on-state SILC, the near-zero SILC, the off-state SILC sensed at lower positive voltages and the one sensed at higher positive voltages. We develop a model of tunnelling assisted by interface states and oxide bulk traps to explain the four different parts of SILC during NBTI stress.     

Effect of heavy ion irradiation on the interface traps of AlGaN/GaN high electron mobility transistors

AlGaN/GaN high electron mobility transistors (HEMTs) were irradiated with heavy ions at various fluences. After irradiation by 2.1 GeV¹⁸¹ Ta³²⁺ ions, the electrical characteristics of the devices significantly decreased. The threshold voltage shifted positively by approximately 25% and the saturation currents decreased by approximately 14%. Defects were induced in the band gap and the interface between the gate and barrier acted as tunneling sites, which increased the gate current tunneling probability. According to the pulsed output characteristics, the amount of current collapse significantly increased and more surface state traps were introduced after heavy ion irradiation. The time constants of the induced surface traps were mainly less than 10 μs.     

Effect of Channel Length and Width on NBTI in Ultra Deep Sub-Micron PMOSFETs

The effects of channel length and width on the degradation of negative bias temperature instability （NBTI） are studied. With the channel length decreasing, the NBTI degradation increases. As tile channel edges have more damage and latent damage for the process reasons, the device can be divided into three parts： the gate and source overlap region, the middle channel region, and the gate and drain overlap region. When the NBTI stress is applied, the non-uniform distribution of the generated defects in the three parts will be generated due to the inhomogeneous degradation. With tile decreasing channel length, tile channel edge regions will take up a larger ratio to the middle channel region and the degradation of NBTI is enhanced. The channel width also plays an important role in the degradation of NBTI. There is an inflection point during the decreasing channel width. There are two particular factors： the lower vertical electric field effect for the thicker gate oxide thickness of the sha/low trench isolation （STI） edge and the STI mechanical stress effecting on the NBTI degradation. The former reduces and the latter intensifies the degradation. Under the mutual compromise of the both factors, when the effect of the STI mechanical stress starts to prevail over the lower vertical electric field effect with the channel width decreasing, the inflection point comes into being.     

The etching of a-plane GaN epilayers grown by metal--organic chemical vapour deposition

Morphology of nonpolar (1120) a-plane GaN epilayers on r-plane (1102) sapphire substrate grown by low-pressure metal-organic vapour deposition was investigated after KOH solution etching. Many micron-and nano-meter columns on the a-plane GaN surface were observed by scanning electron microscopy. An etching mechanism model is proposed to interpret the origin of the peculiar etching morphology. The basal stacking fault in the a-plane GaN plays a very important role in the etching process.     

Degradation mechanism of enhancement-mode AlGaN/GaN HEMTs using fluorine ion implantation under the on-state gate overdrive stress

The degradation mechanism of enhancement-mode Al Ga N/Ga N high electron mobility transistors(HEMTs)fabricated by fluorine plasma ion implantation technology is one major concern of HEMT’s reliability.It is observed that the threshold voltage shows a significant negative shift during the typical long-term on-state gate overdrive stress.The degradation does not originate from the presence of as-grown traps in the Al Ga N barrier layer or the generated traps during fluorine ion implantation process.By comparing the relationships between the shift of threshold voltage and the cumulative injected electrons under different stress conditions,a good agreement is observed.It provides direct experimental evidence to support the impact ionization physical model,in which the degradation of E-mode HEMTs under gate overdrive stress can be explained by the ionization of fluorine ions in the Al Ga N barrier layer by electrons injected from 2DEG channel.Furthermore,our results show that there are few new traps generated in the Al Ga N barrier layer during the gate overdrive stress,and the ionized fluorine ions cannot recapture the electrons.     

Hot carrier injection degradation under dynamic stress

In this paper,we have studied hot carrier injection(HCI) under alternant stress.Under different stress modes,different degradations are obtained from the experiment results.The different alternate stresses can reduce or enhance the HC effect,which mainly depends on the latter condition of the stress cycle.In the stress mode A(DC stress with electron injection),the degradation keeps increasing.In the stress modes B(DC stress and then stress with the smallest gate injection) and C(DC stress and then stress with hole injection under V g = 0 V and V d = 1.8 V),recovery appears in the second stress period.And in the stress mode D(DC stress and then stress with hole injection under V g = 1.8 V and V d = 1.8 V),as the traps filled in by holes can be smaller or greater than the generated interface states,the continued degradation or recovery in different stress periods can be obtained.     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and V_h degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.     

New aspects of HCI test for ultra-short channel n-MOSFET devices

Hot carriers injection (HCI) tests for ultra-short channel n-MOSFET devices were studied. The experimental data of short channel devices (75--90\,nm), which does not fit formal degradation power law well, will bring severe error in lifetime prediction. This phenomenon usually happens under high drain voltage ($V_{\rm d}$) stress condition. A new model was presented to fit the degradation curve better. It was observed that the peak of the substrate current under low drain voltage stress cannot be found in ultra-short channel device. Devices with different channel lengths were studied under different $V_{\rm d}$ stresses in order to understand the relations between peak of substrate current ($I_{\rm sub}$) and channel length/stress voltage.