Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel

We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure(named as MONOS), utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at +11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s' retention. In addition, the leakage current density is lower than 2.52 × 10~(-7) A·cm~(-2) below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics.     

Atomic-layer-deposited Al_2O_3 and HfO_2 on InAlAs: A comparative study of interfacial and electrical characteristics

Al_2O_3 and HfO_2 thin films are separately deposited on n-type InAlAs epitaxial layers by using atomic layer deposition(ALD).The interfacial properties are revealed by angle-resolved x-ray photoelectron spectroscopy(AR-XPS).It is demonstrated that the Al_2O_3 layer can reduce interfacial oxidation and trap charge formation.The gate leakage current densities are 1.37×10~6 A/cm~2 and 3.22×10~6 A/cm~2 at+1V for the Al_2O_3/InAlAs and HfO_2/InAlAs MOS capacitors respectively.Compared with the HfO_2/InAlAs metal-oxide-semiconductor(MOS) capacitor,the Al_2O_3/InAlAS MOS capacitor exhibits good electrical properties in reducing gate leakage current,narrowing down the hysteresis loop,shrinking stretch-out of the C-V characteristics,and significantly reducing the oxide trapped charge(Q_(ot)) value and the interface state density(D_(it)).     

Charge trapping memory device based on the Ga_2O_3 films as trapping and blocking layer

We present a new charge trapping memory(CTM) device with the Au/Ga_2O_3/SiO_2/Si structure, which is fabricated by using the magnetron sputtering, high-temperature annealing, and vacuum evaporation techniques. Transmission electron microscopy diagrams show that the thickness of the SiO_2 tunneling layer can be controlled by the annealing temperature.When the devices are annealed at 760℃, the measured C–V hysteresis curves exhibit a maximum 6 V memory window under a ±13 V sweeping voltage. In addition, a slight degradation of the device voltage and capacitance indicates the robust retention properties of flat-band voltage and high/low state capacitance. These distinctive advantages are attributed to oxygen vacancies and inter-diffusion layers, which play a critical role in the charge trapping process.     

The charge storage characteristics of ZrO2 nanocrystallite-based charge trap nonvolatile memory

ZrO2 nanocrystallite-based charge trap flash memory capacitors incorporating a(ZrO2)0.6(SiO2)0.4 pseudobinary high-k oxide film as the charge trapping layer were prepared and investigated.The precipitation reaction in the charge trapping layer,forming ZrO2 nanocrystallites during rapid thermal annealing,was investigated by transmission electron microscopy and X-ray diffraction.It was observed that a ZrO2 nanocrystallite-based memory capacitor after post-annealing at 850℃ for 60s exhibits a maximum memory window of about 6.8V,good endurance and a low charge loss of ～25% over a period of 10 years(determined by extrapolating the charge loss curve measured experimentally),even at 85℃.Such 850℃-annealed memory capacitors appear to be candidates for future nonvolatile flash memory device applications.     

The Distinguished Charge-Trapping Capability of the Memory Device with Al2O3-Cu2O Composite as the Charge Storage Layer

A memory device Si/Al2O3/Al2O3-Cu2O/Al2O3/Pt is fabricated by using atomic layer deposition and r~magnetron sputtering techniques. The memory device including the composite of Al2O3 and Cu2O as the charge storage layer shows a distinguished charge trapping capability. At a working voltage of ±11 V a memory window of 9.22 V is obtained. The x-ray photoelectron spectroscopic study shows a shoulder from Cu2＋ ions around the peak of Cu1＋ ions. It is suggested that the charge-trapping mechanism should be attributed to the defect states formed by the inter-diffusion at the interface of two oxides.     

Organic field-effect transistor floating-gate memory using polysilicon as charge trapping layer

In this study, we present an organic field-effect transistor floating-gate memory using polysilicon(poly-Si) as a charge trapping layer. The memory device is fabricated on a N~+–Si/SiO_2 substrate. Poly-Si, polymethylmethacrylate, and pentacene are used as a floating-gate layer, tunneling layer, and active layer, respectively. The device shows bidirectional storage characteristics under the action of programming/erasing(P/E) operation due to the supplied electrons and holes in the channel and the bidirectional charge trapping characteristic of the poly-Si floating-gate. The carrier mobility and switching current ratio(Ion/Ioff ratio) of the device with a tunneling layer thickness of 85 nm are 0.01 cm~2·V~(-1)·s~(-1) and 102, respectively. A large memory window of 9.28 V can be obtained under a P/E voltage of ±60 V.     

Surface-type nonvolatile electric memory elements based on organic-on-organic CuPc-H_2Pc heterojunction

A novel surface-type nonvolatile electric memory elements based on organic semiconductors Cu Pc and H2 Pc are fabricated by vacuum deposition of the Cu Pc and H2 Pc films on preliminary deposited metallic(Ag and Cu) electrodes.The gap between Ag and Cu electrodes is 30–40 μm. For the current–voltage(I–V) characteristics the memory effect,switching effect, and negative differential resistance regions are observed. The switching mechanism is attributed to the electric-field-induced charge transfer. As a result the device switches from a low to a high-conductivity state and then back to a low conductivity state if the opposite polarity voltage is applied. The ratio of resistance at the high resistance state to that at the low resistance state is equal to 120–150. Under the switching condition, the electric current increases~80–100times. A comparison between the forward and reverse I–V characteristics shows the presence of rectifying behavior.     

Improvement of the high-k/Ge interface thermal stability using an in-situ ozone treatment characterized by conductive atomic force microscopy

In this work, an in-situ ozone treatment is carried out to improve the interface thermal stability of HfO_2/Al_2O_3 gate stack on germanium(Ge) substrate. The micrometer scale level of HfO_2/Al_2O_3 gate stack on Ge is studied using conductive atomic force microscopy(AFM) with a conductive tip. The initial results indicate that comparing with a non insitu ozone treated sample, the interface thermal stability of the sample with an in-situ ozone treatment can be substantially improved after annealing. As a result, void-free surface, low conductive spots, low leakage current density, and relative high breakdown voltage high-κ/Ge are obtained. A detailed analysis is performed to confirm the origins of the changes.All results indicate that in-situ ozone treatment is a promising method to improve the interface properties of Ge-based three-dimensional(3D) devices in future technology nodes.     

Influence of Post-Annealing on Electrical Characteristics of Thin-Film Transistors with Atomic-Layer-Deposited ZnO-Channel/Al_2O_3-Dielectric

High-performance thin-film transistors(TFTs) with a low thermal budget are highly desired for flexible electronic applications.In this work,the TFTs with atomic layer deposited ZnO-channel/Al_2O_3-dielectric are fabricated under the maximum process temperature of 200℃.First,we investigate the effect of post-annealing environment such as N_2,H_2-N_2(4%) and O_2 on the device performance,revealing that O_2 annealing can greatly enhance the device performance.Further,we compare the influences of annealing temperature and time on the device performance.It is found that long annealing at 200℃ is equivalent to and even outperforms short annealing at 300℃.Excellent electrical characteristics of the TFTs are demonstrated after O_2 annealing at 200℃ for 35 min,including a low off-current of 2.3 × 10~(-13) A,a small sub-threshold swing of 245mV/dec,a large on/off current ratio of 7.6×10~8,and a high electron effective mobility of 22.1cm~2/V·s.Under negative gate bias stress at — 10 V,the above devices show better electrical stabilities than those post-annealed at 300℃.Thus the fabricated high-performance ZnO TFT with a low thermal budget is very promising for flexible electronic applications.     

Memory Effect of Metal--Insulator--Silicon Capacitors with SiO2/HfO2/Al2O3 Dielectrics

Charge trapping characteristics of the metal-insulator-silicon （MIS） capacitors with Si02/HfO2//A12O3 stacked dielectrics are investigated for memory applications＇. A capacitance-voltage hysteresis memory window as large as 7.3 V is achieved for the gate voltage sweeping of ±12 V, and a fiat-band voltage shift of 1.5 V is observed in terms of programming under 5 V and I ms. Furthermore, the time- and voltage-dependent charge trapping characteristics are also demonstrated, the former is related to charge trapping saturation and the latter is ascribed to variable tunnelling barriers for electron injecting and discharging under different voltages.     

Formation of high density TiN nanocrystals and its application in non-volatile memories

Non-volatile memory based on TiN nanocrystal （TiN-NC） charge storage nodes embedded in SiO2 has been fabricated and its electrical properties have been measured. It was found that the density and size distribution of TiN-NCs can be controlled by annealing temperature. The formation of well separated crystalline TiN nano-dots with an average size of 5 nm is confirmed by transmission electron microscopy and x-ray diffraction, x-ray photoelectron spectroscopy confirms the existence of a transition layer of TiNxOy/SiON oxide between TiN-NC and SiO2, which reduces the barrier height of tunnel oxide and thereby enhances programming/erasing speed. The memory device shows a memory window of 2.5V and an endurance cycle throughout 10^5. Its charging mechanism, which is interpreted from the analysis of programming speed （dVth/dt） and the gate leakage versus voltage characteristics （Ig vs Vg）, has been explained by direct tunnelling for tunnel oxide and Fowler Nordheim tunnelling for control oxide at programming voltages lower than 9V, and by Fowler-Nordheim tunnelling for both the oxides at programming voltages higher than 9V.     

Performance improvement of charge trap flash memory by using a composition-modulated high-k trapping layer

A composition-modulated （HfO2）x（Al2O3）1-x charge trapping layer is proposed for charge trap flash memory by controlling the A1 atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated （HfO2）x（Al2O3）l-x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application.     

Improved performance of Au nanocrystal nonvolatile memory by N_2-plasma treatment on HfO_2 blocking layer

The N_2-plasma treatment on a HfO_2 blocking layer of Au nanocrystal nonvolatile memory without any post annealing is investigated. The electrical characteristics of the MOS capacitor with structure of Al–Ta N/HfO_2/Si O2/p-Si are also characterized. After N_2-plasma treatment, the nitrogen atoms are incorporated into HfO_2 film and may passivate the oxygen vacancy states. The surface roughness of HfO_2 film can also be reduced. Those improvements of HfO_2 film lead to a smaller hysteresis and lower leakage current density of the MOS capacitor. The N_2-plasma is introduced into Au nanocrystal(NC) nonvolatile memory to treat the HfO_2 blocking layer. For the N_2-plasma treated device, it shows a better retention characteristic and is twice as large in the memory window than that for the no N_2-plasma treated device. It can be concluded that the N_2-plasma treatment method can be applied to future nonvolatile memory applications.     

Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed.The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing(P/E) operations at various P/E voltages are discussed.The simulated results show that present memory exhibits a large memory window of 57.5 V,and a high read current on/off ratio of ≈ 10~3.Compared with the reported experimental results,these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects,which shows great promise in device designing and practical application.     

High performance lateral Schottky diodes based on quasi-degenerated Ga_2O_3

Ni/β-Ga_2 O_3 lateral Schottky barrier diodes(SBDs) were fabricated on a Sn-doped quasi-degenerate n~+-Ga_2 O_3(201)bulk substrate. The resultant diodes with an area of 7.85 ×10~(-5) cm~2 exhibited excellent rectifying characteristics with an ideality factor of 1.21, a forward current density(J) of 127.4 A/cm2 at 1.4 V, a specific on-state resistance(R_(on,sp)) of1.54 mΩ·cm~2,and an ultra-high on/off ratio of 2.1 ×10~(11) at±1 V. Due to a small depletion region in the highly-doped substrate, a breakdown feature was observed at-23 V, which corresponded to a breakdown field of 2.1 MV/cm and a power figure-of-merit(VB2/R_(on)) of 3.4×10~5 W/cm~2. Forward current-voltage characteristics were described well by the thermionic emission theory while thermionic field emission and trap-assisted tunneling were the dominant transport mechanisms at low and high reverse biases, respectively, which was a result of the contribution of deep-level traps at the metal-semiconductor interface. The presence of interfacial traps also caused the difference in Schottky barrier heights of 1.31 eV and 1.64 eV respectively determined by current-voltage and capacitance-voltage characteristics. With reduced trapping effect and incorporation of drift layers, the β-Ga_2 O_3 SBDs could further provide promising materials for delivering both high current output and high breakdown voltage.     

Memory Effect of Metal-Oxide-Silicon Capacitors with Self-Assembly Double-Layer Au Nanocrystals Embedded in Atomic-Layer-Deposited HfO2 Dielectric

We report the chemical self-assembly growth of Au nanocrystals on atomic-layer-deposited HfO2 films aminosilanized by （3-Aminopropyl）-trimethoxysilane aforehand for memory applications. The resulting Au nanocrystals show a density of about 4 × 10^11 cm^-2 and a diameter range of 5-8nm. The metal-oxide-silicon capacitor with double-layer Au nanocrystals embedded in HfO2 dielectric exhibits a large C - V hysteresis window of 11.9 V for ±11 V gate voltage sweeps at 1MHz, a flat-band voltage shift of 1.5 V after the electrical stress under 7 V for 1ms, a leakage current density of 2.9 × 10^-8 A/cm^-2 at 9 V and room temperature. Compared to single-layer Au nanocrystals, the double-layer Au nanocrystals increase the hysteresis window significantly, and the underlying mechanism is thus discussed.     

Robust Low Voltage Program-Erasable Cobalt-Nanocrystal Memory Capacitors with Multistacked Al2O3/HfO2/Al2O3 Tunnel Barrier

A n atomic-layer-deposited Al2O3/HfO2/Al2O3 （A/H/A） tunnel barrier is in vestigated for Co nanocrystal memory capacitors. Compared to a single Al2O3 tunnel barrier, the A/H/A barrier can significantly increase the hysteresis window, i.e., an increase by 9 V for ±12 V sweep range. This is attributed to a marked decrease in the energy barriers of charge injections for the A/H/A tunnel barrier. Further, the Co-nanocrystal memory capacitor with the A/H/A tunnel barrier exhibits a memory window as large as 4.1 V for 100 μs program/erase at a low voltage of ±7 V, which is due to fast charge injection rates, i.e., about 2.4× 10^16 cm^-2 s^-1 for electrons and 1.9× 1016 cm^-2 s^-1 for holes.     

A Base-Emitter Self-Aligned Multi-Finger Sil-xGex/Si Power Heterojunction Bipolar Transistor

With a crystal orientation dependent on the etch rate of Si in KOH-based solution, a base-emitter self-Migned large-area multi-finger configuration power SiGe heterojunction bipolar transistor （HBT） device （with an emitter area of about 880μm^2） is fabricated with 2μm double-mesa technology. The maximum dc current gain is 226.1. The collector-emitter junction breakdown voltage BVcEo is 10 V and the collector-base junction breakdown voltage BVcBo is 16 V with collector doping concentration of 1 × 10^17 cm^-3 and thickness of 400nm. The device exhibited a maximum oscillation frequency fmax of 35.5 GHz and a cut-off frequency fT of 24.9 GHz at a dc bias point of Ic = 70 mA and the voltage between collector and emitter is VCE = 3 V. Load pull measurements in class-A operation of the SiGe HBT are performed at 1.9 GHz with input power ranging from OdBm to 21 dBm. A maximum output power of 29.9dBm （about 977mW） is obtained at an input power of 18.SdBm with a gain of 11.47dB. Compared to a non-self-aligned SiGe HBT with the same heterostructure and process, fmax and fT are improved by about 83.9% and 38.3%, respectively.     

Realization of Ultraviolet Electroluminescence from ZnO Homojunction Fabricated on Silicon Substrate with p-Type ZnO:N Layer Formed by Radical N2O Doping

ZnO homojunction light-emitting diodes are fabricated on Si（100） substrates by plasma assisted metal organic chemical vapour deposition. A p-type layer of nitrogen-doped ZnO film is formed using radical N2O as the acceptor precursor. The n-type ZnO layer is composed of un-doped ZnO film. The device exhibits desirable rectifying behaviour with a turn-on voltage of 3.3 V and a reverse breakdown voltage higher than 6 V. Distinct electrolumineseence emissions centred at 395nm and 490nm are detected from this device at forward current higher than 20mA at room temperature.     

β-Ga_2O_3 MOSFETs on the Si substrate fabricated by the ion-cutting process

β-Ga_2O_3 MOSFETs are demonstrated on heterogeneous Ga_2O_3-Al_2O_3-Si(GaOISi)substrate fabricated by ion-cutting process.Enhancement(E)-and depletion(D)-modeβ-Ga_2O_3 transistors are realized on by varying the channel thickness(T_(ch)).E-mode GaOISi transistor with a T_(ch)of 15 nm achieves a high threshold voltage V_(TH)of～8 V.With the same T increase,GaOISi transistors demonstrate more stable ON-current I_(ON)and OFF-current I_(OFF)performance compared to the reported devices on bulk Ga_2O_3 wafer.Transistors on GaOISi achieve the breakdown voltage of 522 and 391 V at 25°C and 200°C,respectively.