Research on total-dose hardening for H-gate PD NMOSFET/SIMOX by ion implanting into buried oxide

In this work,we investigate the back-gate I-V characteristics for two kinds of NMOSFET/SIMOX transistors with H gate structure fabricated on two different SOI wafers.A transistors are made on the wafer implanted with Si+ and then annealed in N2,and B transistors are made on the wafer without implantation and annealing.It is demonstrated experimentally that A transistors have much less back-gate threshold voltage shift AVth than B transistors under X-ray total dose irradiation.Subthreshold charge separation technique is employed to estimate the build-up of oxide charge and interface traps during irradiation,showing that the reduced △Vth for A transistors is mainly due to its less build-up of oxide charge than B transistors.Photoluminescence (PL) research indicates that Si implantation results in the formation of silicon nanocrystalline (nanocluster) whose size increases with the implant dose.This structure can trap electrons to compensate the positive charge build-up in the buried oxide during irradiation,and thus reduce the threshold voltage negative shift.     

氮氟复合注入对注氧隔离SOI材料埋氧层内固定正电荷密度的影响

为了抑制埋层注氮导致的埋层内正电荷密度的上升, 本文采用氮氟复合注入方式, 向先行注氮的埋层进行了注氮之后的氟离子注入, 并经适当的退火, 对埋层进行改性. 利用高频电容-电压 (C-V) 表征技术, 对复合注入后的埋层进行了正电荷密度的表征. 结果表明, 在大多数情况下, 氮氟复合注入能够有效地降低注氮埋层内的正电荷密度, 且其降低的程度与注氮后的退火时间密切相关. 分析认为, 注氟导致注氮埋层内的正电荷密度降低的原因是在埋层中引入了与氟相关的电子陷阱. 另外, 实验还观察到, 在个别情况下, 氮氟复合注入引起了埋层内正电荷密度的进一步上升. 结合测量结果, 讨论分析了该现象产生的原因. 关键词： 绝缘体上硅(SOI) 材料 注氮 注氟 埋氧层正电荷密度     

Improvement of total-dose irradiation hardness of silicon-on-insulator materials by modifying the buried oxide layer with ion implantation

The hardening of the buried oxide (BOX) layer of separation by implanted oxygen (SIMOX) silicon-on-insulator (SOI) wafers against total-dose irradiation was investigated by implanting ions into the BOX layers. The tolerance to total-dose irradiation of the BOX layers was characterized by the comparison of the transfer characteristics of SOI NMOS transistors before and after irradiation to a total dose of 2.7 Mrad(SiO₂. The experimental results show that the implantation of silicon ions into the BOX layer can improve the tolerance of the BOX layers to total-dose irradiation. The investigation of the mechanism of the improvement suggests that the deep electron traps introduced by silicon implantation play an important role in the remarkable improvement in radiation hardness of SIMOX SOI wafers.     

Interface modification and trap-type transformation in Al-doped CdO/Si-nanowire arrays/p-type Si devices by nanowire surface passivation

The present work reports the fabrication and detailed electrical properties of Al-doped CdO/Si-nanowire (SiNW) arrays/p-type Si Schottky diodes with and without SiNW surface passivation. It is shown that the interfacial trap states influence the electronic conduction through the device. The experimental results demonstrate that the effects of the dangling bonds at the SiNW surface and Si vacancies at the SiO_x/SiNW interface which can be changed by the Si–O bonding on the energy barrier lowering and the charge transport property. The induced dominance transformation from electron traps to hole traps in the SiNWs by controlling the passivation treatment time is found in this study.     

Er3+注入CdTe薄膜的结构和光电性能研究

采用离子注入技术对近距离升华制备的CdTe薄膜进行Er³⁺掺杂研究.讨论了不同掺Er³⁺浓度对CdTe薄膜的结构和光电性能的影响.利用X射线衍射仪、扫描电子显微镜、紫外-可见分光光度计、霍耳效应测试系统和复阻抗分析仪对样品进行测试.结果表明，适当的掺杂量可以改善CdTe薄膜的结晶性能，降低晶界势垒高度，提高其导电性能.在一定掺杂范围内掺Er³⁺对CdTe薄膜的光能隙影响不大. 关键词： CdTe薄膜 离子注入 晶界势垒 光能隙     

Carrier transport and photoresponse for heterojunction diodes based on the reduced graphene oxide-based TiO2 composite and p-type Si

The present work reports the fabrication and detailed electrical properties of heterojunction diodes based on p-type Si and the reduced graphene oxide-based TiO₂ (TiO₂:RGO) composite. The enhanced dark conductivity was observed for TiO₂:RGO composite films. The improved electrical conductivity is considered to mainly come from the mobility enhancement. The TiO₂/p-type Si diode shows a poor rectifying behavior and low photoresponse. This is because of the dominance of electron traps in TiO₂. However, the TiO₂:RGO/p-type Si diode shows a good rectifying behavior and high photoresponse, which is attributed to high-mobility electron transport combined with the reduced number of electron traps.     

Effect of implantation energy and dose on low-dose SIMOX structures

In order to form silicon (Si)-on-insulator (SOI) layers with various thicknesses, oxygen implantation with doses between 1.0×10¹⁷/cm² and 6.0×10¹⁷/cm² and at energies between 40 and 240 keV has been carried out into 300 mm diameter (100)Si wafers at a temperature of 560 °C. After implantation, Si wafers are annealed in dry Ar mixed with 1% O₂ at a temperature of 1350 °C for 4 h. The quality of buried oxide (BOX) layers and the microstructure in implanted layers before and after annealing is characterized by transmission electron microscopy. The results reveal that the appreciable number of threading dislocations (TDs) is generated in SOI layers implanted at energies above 200 keV under the optimum dose-energy conditions for the continuous BOX layer formation. Whereas, in the case of discontinuous BOX layers, the TD generation is observed in samples implanted at energies above 120 keV. The generation of TDs is discussed with the emphasis on the effect of implantation energy. PACS 61.72Ff; 61.72Lk     

Interaction of cesium with charged oxide under UV irradiation imaged by photoemission electron microscopy

We report the first observation of electron transfer from charged SiO₂/Si(1 0 0) by ion-implantation via internal photoemission from Si by photoemission electron microscopy (PEEM) for the purpose of the microscopic control of promotion of catalyst by electron transfer from oxide support. The contrast of the PEEM image varies with the amount and kind of the implanted ion and the deposition of Cs through the formation of electrical double layer consisting of Cs⁺ and trapped electrons at trapping centers created by the implantation. It is then firmly established that oxide charging can be microscopically tuned by ion-implantation.     

Novel approaches for low cost fabrication of SOI

Two trials for low cost manufacture of silicon-on-insulator (SOI) wafers were implemented. Low dose separation by implantation of oxygen (SIMOX) procedure has been conducted on a beam-line ion implanter with mass analyzer. The energy dependence of the formed SOI structure was studied at varied implant dosages. The integrity of the buried oxide (BOX) layer was examined by transmission electron microscopy (TEM) and the threading dislocation in the top silicon layer was evaluated by Secco technique. The results indicated that not only the implanted oxygen dose but also the oxygen ion energy plays an important role in the formation of SOI structure with good crystallinity of top silicon, sharp Si/SiO₂ interfaces and highly integrated BOX layer free of silicon inclusion. For separation by plasma implantation of oxygen (SPIMOX) approach, water plasma, rather than oxygen plasma, was employed to avoid oxygen spread in the implant depth profile. The SPIMOX process using water plasma was carried out on a beam-line ion implanter without mass selector to simulate the plasma implantation procedure. Cross-sectional TEM study revealed that uniform BOX layer was formed under single crystal silicon superficial layer with the present approach. The interfaces between silicon superficial layer, BOX layer and bulk silicon were smooth and sharp. An implant dose window has been identified for fabricating the desirable SOI structure.     

Deep Level Transient Spectroscopy of Defects in High-Energy Light-Particle Irradiated Si

The authors review what has been learned concerning the electrical and annealing properties of point defects in high-energy electron or proton irradiated Si from deep level transient spectroscopy (DLTS). The authors have focused mainly on the properties of electron traps, and to a lesser extent on the properties of hole traps. In addition to an in-depth discussion of hydrogen-related defects in Si, this review article provides a brief tutorial on ion-solid interactions and the theory underlying DLTS. The authors also provide a few examples of the power of high resolution Laplace DLTS in analyzing radiation induced defects. The collection of results gathered in this article may provide the fundamental information for successful defect engineering in light-particle irradiated Si.     

Transient behavior of the strong violet electroluminescence of Ge-implanted SiO2 layers

Si-based light emitters will be a key element of future optoelectronics. One of the most promising approaches is Ge implantation into thin SiO₂ films on crystalline Si. This system exhibits a strong violet electroluminescence with a power efficiency up to 0.5% [18], but the mechanism of electrical excitation is not yet fully understood. In this paper the electrical excitation of the luminescence centers is investigated by means of electrical and electroluminescence transient measurements. It is found that the most probable way to excite luminescence centers is the impact excitation by hot electrons. Whereas the injection is explained by trap-assisted tunneling of electrons from the substrate into the oxide, the electrons will be transported via traps or in the SiO₂ conduction band. Furthermore, the electroluminescence rise and decay time is estimated to be of the order of 100 μs. Received: 26 September 2001 / Published online: 29 November 2001     

Electrical generation of pure spin current with oscillating spin-orbit interaction

We propose an electrical scheme for the generation of a pure spin current without a charge current in a two-terminal device, which consists of a scattering region of a two-dimensional electron gas (2DEG) with Rashba (R) and/or Dresselhaus (S) spin-orbit interaction (SOI) and two normal leads. The SOI is modulated by a time-dependent gate voltage to pump a spin current. Based on a tight-binding model and the Keldysh Green’s function technique, we obtain the analytical expression of the spin current. It is shown that a pure spin current can be pumped out, and its magnitude could be modulated by device parameters such as the oscillating frequency of the SOI, as well as the SOI strength. Moreover, the spin polarisation direction of the spin current could also be tuned by the strength ratio between RSOI and DSOI. Our proposal provides not only a fully electrical means to generate a pure spin current but also a way to control the spin polarisation direction of the generated spin current.     

Phenomena in silicon nanostructure devices

In nanostructures, whenever the electron mean-free-path exceeds the appropriate dimensions of the device structure, quantum natures may dictate the physical properties of devices. Among many important issues, some are selected in this work, whereas others, such as the reduction of dielectric constant, the increased binding energy of dopants, etc., are discussed briefly with references for further considerations. In the past several years, resonant tunneling via nanoscale silicon particles imbedded in an oxide matrix has shown striking similarity to the so-called soft breakdown (SBD), an important current subject in devices with ultrathin oxide gates. The relevance in applying results discussed here to SBD is discussed. A Si/O superlattice, a particular form of a new type of superlattice, semiconductor-atomic superlattice (SAS), is fully discussed. This Si/O superlattice can be used in silicon quantum and light-emitting devices. A diode structure with green electroluminescence has been life-tested for more than one year without degradation. High-resolution TEM shows defect density below 10⁹/cm². Preliminary calculation shows that the Si/O complexes result in a barrier height of 0.9 eV for silicon, sufficient for an epitaxially grown SOI, which is potentially far better than the SOI using buried oxide implantation followed by high temperature anneal. Received: 14 April 2000 / Accepted: 17 April 2000 / Published online: 6 September 2000     

体硅、SOI及DSOI MOSFET器件级电、热分析

利用简化的半导体电学方程,数值模拟获得了各种电学参数的分布,并结合简化电阻模型,模拟了体硅、SOI及DSOI的MOSFET器件的温度场。结果表明MOSFET器件的沟道,特别是靠近漏的区域电场强度及电流密度等各项电、热特性参数在该区域变化剧烈,是最主要的热源区。     

Epitaxial growth of fully relaxed Si0.75Ge0.25 on SOI substrate

A fully relaxed Si_0.75Ge_0.25 film with low dislocation densities is fabricated by epitaxial growth on SOI substrate without depositing graded buffers. The relaxation mechanism of the SiGe layer directly grown on SOI substrate is also analyzed. For SiGe grown on SOI with low Ge content, the strain is redistributed between SiGe and the top Si of SOI substrate, and the strain residing in SiGe layer can be fully relaxed by the formation and expansion of dislocation half-loops near the SiGe/Si interface. The surface morphology and crystal quality of all samples are analyzed by optical microscopy and transmission electron microscopy (TEM), respectively. Compared to the Si_0.75Ge_0.25 layer epitaxially grown on graded buffer, the Si_0.75Ge_0.25 directly grown on SOI substrate appears good surface morphology and perfect crystal quality.     

Stress-induced leakage currents of the RF sputtered Ta2O5 on N-implanted silicon

The electrical (C-V and I-V) and reliability (constant current stress technique) properties of RF sputtered 30 nm thick Ta₂O₅ on N-implanted Si have been investigated. The dependence on the parameters of both Ta₂O₅ and the implanted interfacial layers on the stress time are discussed. The leakage current characteristics are analyzed by previously proposed comprehensive model. It is established that the reliability of the Ta₂O₅-based capacitors can be effectively improved if the Si substrate is a subject to preliminary N-implantation—markedly smaller stress induced leakage current as compared to the films on bare Si are detected. The stress mainly affects the properties of the interfacial layer and the generation of neutral traps is identified to be the primary cause for the stress-induced degradation. It is concluded that the implantation results in a strengthening of the interfacial layer against stress degradation.     

Reduced self-heating by strained silicon substrate engineering

Substrate engineering innovations such as SOI and the use of Si/SiGe virtual substrates become necessary in order to maintain performance leverage of integrated circuits with continued scaling. The relevance of thermal effects in device design increases since the thermal conductivity of these new materials is poor. The electrical performance of devices fabricated on thin virtual substrates grown by two different techniques is presented. It is found that self-heating is reduced and that thermal resistance measurements agree with modelling predictions. The reduction in performance enhancement seen in many strained Si MOSFETs is found here to be largely due to self-heating effects, rather than parasitics or the loss of strain.     

一种新型Si/SiGe/Si双异质结PIN电学调制结构的异质结能带分析

PIN结构是电光调制器中常见的一种电学调制结构, 该结构中载流子注入效率直接影响着电光调制器的性能. 在前期的研究中, 我们在SOI材料的基础上提出了一种新型Si/SiGe/Si双异质结PIN电学调制结构, 可以有效提高载流子注入效率, 降低调制功耗. 为了进一步研究这种新型调制器结构的调制机理, 本文从单异质结能带理论出发, 定量分析了该新型结构中双异质结的势垒高度变化, 给出了双异质结势垒高度的定量公式, 将新型结构与SiGe-OI和SOI两种PIN电学调制结构进行能带对比, 分析了该新型结构载流子注入增强的原因, 最后模拟了新型结构的能带分布, 以及能带和调制电压与注入载流子密度的关系, 并与SiGe-OI和SOI两种PIN电学调制结构进行对比发现, 1 V调制电压下, 新型结构的载流子密度达到了8× 10¹⁸cm^-3, 比SOI 结构的载流子密度高了800%, 比SiGe-OI结构的载流子密度高了340%, 进一步说明了该新型结构的优越性, 并且验证了理论分析的正确性.     

Effect of High Temperature—Pressure on Buried Silicon Dioxide in Simox and Soi Structures

The effect of annealing at 1520–1570 K under high pressure (HP, up to 1.2GPa) on the structure of SiO₂ in oxygen implanted silicon (Si:O) and in silicon with buried SiO₂ layer (SOI) was investigated by TEM, X-Ray and FTIR methods. Depending on the implantation and treatment parameters, SiO₂ precipitates or continuous SiO₂ layers, sometimes with defects at the SiO₂/Si boundary, are created. A stress dependent shift of asymmetric stretching vibration mode associated with Si-O bonds towards lower frequencies is detected for SiO₂ in the HT—HP treated Si:O and SOI samples.     

Comparative study of low frequency noise and hot-carrier reliability in SiGe PD SOI pMOSFETs

The stress effect of SiGe pMOSFETs has been investigated to understand the electrical properties of devices fabricated on the Si bulk and PD SOI substrates. A comparison of the drain saturation current (I_D.sat) and maximum transconductance (g_m,max) in both the SiGe bulk and the SiGe PD SOI devices clearly shows that the SiGe PD SOI is more immune from hot-carriers than the SiGe bulk. The stress-induced leakage current (SILC) is hardly detectable in ultra-thin oxide, because the increasing contribution of direct tunneling is comparable to the trap-assisted component. The SiGe PD SOI revealed degraded properties being mainly associated with the detrimental silicon-oxide interface states of the SOI structure.