Impact of O_2 post oxidation annealing on the reliability of SiC/SiO_2 MOS capacitors |
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| Institution: | 1.Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;2.University of Chinese Academy of Sciences, Beijing 100049, China;3.High-Frequency High-Voltage Device and Integrated Circuits R&D Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China |
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| Abstract: | The effects of dry O_2 post oxidation annealing(POA) at different temperatures on SiC/SiO_2 stacks are comparatively studied in this paper. The results show interface trap density(Dit) of SiC/SiO_2 stacks, leakage current density(Jg), and time-dependent dielectric breakdown(TDDB) characteristics of the oxide, are affected by POA temperature and are closely correlated. Specifically, Dit, Jg, and inverse median lifetime of TDDB have the same trend against POA temperature, which is instructive for SiC/SiO_2 interface quality improvement. Moreover, area dependence of TDDB characteristics for gate oxide on SiC shows different electrode areas lead to same slope of TDDB Weibull curves. |
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| Keywords: | SiC O2 post oxidation annealing interface traps MOS |
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