Snapback应力引起的90 nm NMOSFET's栅氧化层损伤研究

实验结果发现突发击穿(snapback)，偏置下雪崩热空穴注入NMOSFET栅氧化层，产生界面态，同时空穴会陷落在氧化层中.由于栅氧化层很薄，陷落的空穴会与隧穿入氧化层中的电子复合形成大量中性电子陷阱，使得栅隧穿电流不断增大.这些氧化层电子陷阱俘获电子后带负电，引起阈值电压增大、亚阈值电流减小.关态漏泄漏电流的退化分两个阶段：第一阶段亚阈值电流是主要成分，第二阶段栅电流是主要成分.在预加热电子(HE)应力后，HE产生的界面陷阱在snapback应力期间可以屏蔽雪崩热空穴注入栅氧化层，使器件snapback开态和关态特性退化变小. 关键词： 突发击穿 软击穿 应力引起的泄漏电流 热电子应力     

超薄栅氧化层n-MOSFET软击穿后的导电机制

研究了恒压应力下超薄栅氧化层n型金属-氧化物-半导体场效应晶体管（n-MOSFET）软击穿 后的导电机制.发现在一定的栅电压V_g范围内，软击穿后的栅电流I_g符合Fowl er-Nordheim隧穿公式，但室温下隧穿势垒_b的平均值仅为0936eV，远小于S i/Si O₂界面的势垒高度315eV.研究表明，软击穿后，处于Si/SiO₂界 面量子化能级上的 电子不隧穿到氧化层的导带，而是隧穿到氧化层内的缺陷带上._b与缺陷带能 级和电 子所处的量子能级相关；高温下，激发态电子对隧穿电流贡献的增大导致_b逐 渐降低. 关键词： 软击穿 栅电流 类Fowler-Nordheim隧穿 超薄栅氧化层     

薄栅氧化层经时击穿的实验分析及物理模型研究

通过衬底热载流子注入技术,对薄SiO₂层击穿特性进行了研究.与通常的F-N应力实验相比较,热载流子导致的薄栅氧化层击穿显示了不同的击穿特性.通过计算注入到氧化层中的电子能量和硅衬底的电场的关系表明,热电子注入和F-N隧穿的不同可以用氧化层中电子的平均能量来解释.热空穴注入的实验结果表明薄栅氧化层的击穿不仅由注入的空穴数量决定.提出了全新的热载流子增强的薄栅氧化层经时击穿模型 关键词： 薄栅氧化层 经时击穿 衬底热载流子 击穿电荷 模型     

电压应力下超薄栅氧化层n-MOSFET的击穿特性

研究了90nm工艺下栅氧化层厚度为1.4nm的n-MOSFET的击穿特性，包括V-ramp(斜坡电压)应力下器件栅电流模型和CVS(恒定电压应力)下的TDDB(经时击穿)特性，分析了电压应力下器件的失效和退化机理.发现器件的栅电流不是由单一的隧穿引起，同时还有电子的翻越和渗透.在电压应力下，SiO₂中形成的缺陷不仅降低了SiO₂的势垒高度，而且等效减小了SiO₂的厚度(势垒宽度).另外，每一个缺陷都会形成一个导电通道，这些导电通道的形成增大了栅电流，导致器件性能的退化，同时栅击穿时间变长. 关键词： 超薄栅氧化层 斜坡电压 经时击穿 渗透     

金属氧化物半导体场效应管热载流子退化的1/fγ噪声相关性研究

研究了金属氧化物半导体(MOS)器件在高、中、低三种栅压应力下的热载流子退化效应及其1/fγ噪声特性.基于Si/SiO2界面缺陷氧化层陷阱和界面陷阱的形成理论,结合MOS器件1/f噪声产生机制,并用双声子发射模型模拟了栅氧化层缺陷波函数与器件沟道自由载流子波函数及其相互作用产生能级跃迁、交换载流子的具体过程.建立了热载流子效应、材料缺陷与电参量、噪声之间的统一物理模型.还提出了用噪声参数Sfγ表征高、中、低三种栅应力下金属氧化物半导体场效应管抗热载流子损伤能力的方法.根据热载流子对噪声影响的物理机制设计了实验并验证这个模型.实验结果与模型符合良好.     

原子层沉积Al2O3/n-GaN MOS结构的电容特性

利用原子层沉积技术制备了具有圆形透明电 极的Ni/Au/Al₂O₃/n-GaN金属-氧化物-半导体结构, 研究了紫外光照对样品电容特性及深能级界面态的影响, 分析了非理想样品积累区电容随偏压增加而下降的物理起源. 在无光照情形下, 由于极长的电子发射时间与极慢的少数载流子热产生速率, 样品的室温电容-电压扫描曲线表现出典型的深耗尽行为, 且准费米能级之上占据深能级界面态的电子状态保持不变. 当器件受紫外光照射时, 半导体耗尽层内的光生空穴将复合准费米能级之上的深能级界面态电子, 同时还将与氧化层内部的深能级施主态反应. 非理想样品积累区电容的下降可归因于绝缘层漏电导的急剧增大, 其诱发机理可能是与氧化层内的缺陷态及界面质量有关的“charge-to-breakdown”过程. 关键词： 原子层沉积 2O₃/n-GaN')" href="#">Al₂O₃/n-GaN 金属-氧化物-半导体结构 电容特性     

阶梯AlGaN外延新型Al_(0.25)Ga_(0.75)N/GaNHEMTs击穿特性分析

为了优化AlGaN/GaN HEMTs器件表面电场,提高击穿电压,本文首次提出了一种新型阶梯AlGaN/GaN HEMTs结构.新结构利用AlGaN/GaN异质结形成的2DEG浓度随外延AlGaN层厚度降低而减小的规律,通过减薄靠近栅边缘外延的AlGaN层,使沟道2DEG浓度分区,形成栅边缘低浓度2DEG区,低的2DEG使阶梯AlGaN交界出现新的电场峰,新电场峰的出现有效降低了栅边缘的高峰电场,优化了AlGaN/GaN HEMTs器件的表面电场分布,使器件击穿电压从传统结构的446 V,提高到新结构的640 V.为了获得与实际测试结果一致的击穿曲线,本文在GaN缓冲层中设定了一定浓度的受主型缺陷,通过仿真分析验证了国际上外延GaN缓冲层时掺入受主型离子的原因,并通过仿真分析获得了与实际测试结果一致的击穿曲线.     

动态应力下超薄栅氧化层经时击穿的可靠性评价

实验发现动态电压应力条件下,由于栅氧化层很薄,高电平应力时间内隧穿入氧化层的电子与陷落在氧化层中的空穴复合产生中性电子陷阱,中性电子陷阱辅助电子隧穿.由于每个周期的高电平时间较短(远远低于电荷的复合时间),隧穿到氧化层的电子很少,同时低电平应力时间内一部分电荷退陷,形成的中性电子陷阱更少.随着应力时间的累积,中性电子陷阱达到某个临界值,栅氧化层突然击穿.高电平时形成的陷阱较少和低电平时一部分电荷退陷,使得器件的寿命提高. 关键词： 超薄栅氧化层 斜坡电压 经时击穿     

p型硅MOS结构Si/SiO_2界面及其附近的深能级与界面态

用深能级瞬态谱(DLTS)技术系统研究了Si/SiO_2界面附近的深能级和界面态。结果表明,在热氧化形成的Si/SiO_2界面及其附近经常存在一个浓度很高的深能级,它具有若干有趣的特殊性质,例如它的DLTS峰高度强烈地依赖于温度,以及当栅偏压使费密能级与界面处硅价带顶的距离明显小于深能级与价带顶的距离时,仍然可以观测到一个很强的DLTS峰。另外,用最新方法测量的Si/SiO_2界面连续态的空穴俘获截面与温度有关,而与能量位置无明显关系,DLTS测量的界面态能量分布与准静态C-V测量的结果完全不一致。本文提出的Si/SiO_2界面物理模型能合理地解释上述问题。     

p型硅MOS结构Si/SiO2界面及其附近的深能级与界面态

用深能级瞬态谱(DLTS)技术系统研究了Si/SiO₂界面附近的深能级和界面态。结果表明,在热氧化形成的Si/SiO₂界面及其附近经常存在一个浓度很高的深能级,它具有若干有趣的特殊性质,例如它的DLTS峰高度强烈地依赖于温度,以及当栅偏压使费密能级与界面处硅价带顶的距离明显小于深能级与价带顶的距离时,仍然可以观测到一个很强的DLTS峰。另外,用最新方法测量的Si/SiO₂界面连续态的空穴俘获截面与温度有关,而与能量位置无明显关系,DLTS测 关键词：     

Impact of STI indium implantation on reliability of gate oxide

The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.     

Correlation between Si-SiO2 heterojunction and Fowler-Nordheim conduction mechanism after soft breakdown in ultrathin oxides

A stress-induced defect band model is proposed to investigate the Fowler-Nordheim tunneling characteristics of ultrathin gate oxides after soft breakdown. Soft breakdown occurs when the average distance between stress-induced defects locally reaches a critical value to overlap the bound electron wavefunction on adjacent defects and to form a defect band. This model shows that an n⁺-poly-Si/N-SiO₂/p-Si heterojunction structure is formed between electrodes at a local area after a soft breakdown in the ultrathin SiO₂ and the soft breakdown current can be described in terms of the Fowler-Nordheim tunneling process with a barrier height of ∼1 eV.     

Experimental evaluation of interface states during time-dependent dielectric breakdown of GaN-based MIS-HEMTs with LPCVD-SiN_x gate dielectric

We experimentally evaluated the interface state density of Ga N MIS-HEMTs during time-dependent dielectric breakdown(TDDB). Under a high forward gate bias stress, newly increased traps generate both at the Si Nx/Al Ga N interface and the Si Nx bulk, resulting in the voltage shift and the increase of the voltage hysteresis. When prolonging the stress duration, the defects density generated in the Si Nx dielectric becomes dominating, which drastically increases the gate leakage current and causes the catastrophic failure. After recovery by UV light illumination, the negative shift in threshold voltage(compared with the fresh one) confirms the accumulation of positive charge at the Si Nx/Al Ga N interface and/or in Si Nx bulk, which is possibly ascribed to the broken bonds after long-term stress. These results experimentally confirm the role of defects in the TDDB of Ga N-based MIS-HEMTs.     

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

A multi-deposition multi-annealing technique(MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device's performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown(TDDB) characteristics of positive channel metal oxide semiconductor(PMOS) under different MDMA process conditions, including the deposition/annealing(DA) cycles, the DA time, and the total annealing time. The results show that the increases of the number of DA cycles(from 1 to 2) and DA time(from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail(TTF) at 63.2% increases by about several times. However, too many DA cycles(such as 4 cycles) make the equivalent oxide thickness(EOT) increase by about 1 ?A and the TTF of PMOS worsen. Moreover, different DA times and numbers of DA cycles induce different breakdown mechanisms.     

Impact of O_2 post oxidation annealing on the reliability of SiC/SiO_2 MOS capacitors

The effects of dry O_2 post oxidation annealing(POA) at different temperatures on SiC/SiO_2 stacks are comparatively studied in this paper. The results show interface trap density(Dit) of SiC/SiO_2 stacks, leakage current density(Jg), and time-dependent dielectric breakdown(TDDB) characteristics of the oxide, are affected by POA temperature and are closely correlated. Specifically, Dit, Jg, and inverse median lifetime of TDDB have the same trend against POA temperature, which is instructive for SiC/SiO_2 interface quality improvement. Moreover, area dependence of TDDB characteristics for gate oxide on SiC shows different electrode areas lead to same slope of TDDB Weibull curves.     

Influence of Si/SiO2 interface properties on electrical performance and breakdown characteristics of ultrathin stacked oxide/nitride dielectric films

In this work, the influence of Si/SiO₂ interface properties, interface nitridation and remote-plasma-assisted oxidation (RPAO) thickness (<1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxide/nitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/SiO₂ interface evidenced by less negative V_t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C-V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress.     

Electronic structures and optical properties of rutile TiO2 with different point defects from DFT + U calculations

The electronic states and formation energies of four types of lattice point defects in rutile TiO₂ are studied using the first-principles calculations. The existence of oxygen vacancy leads to a deep donor defect level in the forbidden band, while the Ti interstitial forms two local states. It is predicted that oxygen vacancy prefers to combine with Ti-interstitial to form V_O–Ti_i dimer by a partial 3d electron transfer from the Ti_i to its neighboring V_O. The charge distribution between a Ti interstitial and its neighboring Ti ions partially shields the Coulomb interactions. Lastly, optical properties of these defective lattices are discussed.     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.