Reverse blocking characteristics and mechanisms in Schottky-drain AlGaN/GaN HEMT with a drain field plate and floating field plates

In this paper, a novel Al Ga N/Ga N HEMT with a Schottky drain and a compound field plate(SD-CFP HEMT) is presented for the purpose of better reverse blocking capability. The compound field plate(CFP) consists of a drain field plate(DFP) and several floating field plates(FFPs). The physical mechanisms of the CFP to improve the reverse breakdown voltage and to modulate the distributions of channel electric field and potential are investigated by two-dimensional numerical simulations with Silvaco-ATLAS. Compared with the HEMT with a Schottky drain(SD HEMT) and the HEMT with a Schottky drain and a DFP(SD-FP HEMT), the superiorities of SD-CFP HEMT lie in the continuous improvement of the reverse breakdown voltage by increasing the number of FFPs and in the same fabrication procedure as the SD-FP HEMT.Two useful optimization laws for the SD-CFP HEMTs are found and extracted from simulation results. The relationship between the number of the FFPs and the reverse breakdown voltage as well as the FP efficiency in SD-CFP HEMTs are discussed. The results in this paper demonstrate a great potential of CFP for enhancing the reverse blocking ability in Al Ga N/Ga N HEMT and may be of great value and significance in the design and actual manufacture of SD-CFP HEMTs.     

Mechanism of improving forward and reverse blocking voltages in AlGaN/GaN HEMTs by using Schottky drain

In this paper, we demonstrate that a Schottky drain can improve the forward and reverse blocking voltages(BVs)simultaneously in AlGaN/GaN high-electron mobility transistors(HEMTs). The mechanism of improving the two BVs is investigated by analysing the leakage current components and by software simulation. The forward BV increases from72 V to 149 V due to the good Schottky contact morphology. During the reverse bias, the buffer leakage in the Ohmicdrain HEMT increases significantly with the increase of the negative drain bias. For the Schottky-drain HEMT, the buffer leakage is suppressed effectively by the formation of the depletion region at the drain terminal. As a result, the reverse BV is enhanced from-5 V to-49 V by using a Schottky drain. Experiments and the simulation indicate that a Schottky drain is desirable for power electronic applications.     

Influence of a drain field plate on the forward blocking characteristics of an AlGaN/GaN high electron mobility transistor

In this paper,the influence of a drain field plate(FP)on the forward blocking characteristics of an AlGaN/GaN high electron mobility transistor(HEMT)is investigated.The HEMT with only a gate FP is optimized,and breakdown voltage VBRis saturated at 1085 V for gate–drain spacing LGD≥8μm.On the basis of the HEMT with a gate FP,a drain FP is added with LGD=10μm.For the length of the drain FP LDF≤2μm,VBRis almost kept at 1085 V,showing no degradation.When LDFexceeds 2μm,VBRdecreases obviously as LDFincreases.Moreover,the larger the LDF,the larger the decrease of VBR.It is concluded that the distance between the gate edge and the drain FP edge should be larger than a certain value to prevent the drain FP from affecting the forward blocking voltage and the value should be equal to the LGDat which VBR begins to saturate in the first structure.The electric field and potential distribution are simulated and analyzed to account for the decrease of VBR.     

An AlGaN/GaN HEMT with enhanced breakdown and near-zero breakdown voltage temperature coefficient

An AlGaN/GaN high-electron mobility transistor (HEMT) with a novel source-connected air-bridge field plate (AFP) is experimentally verified. The device features a metal field plate that jumps from the source over the gate region and lands between the gate and drain. When compared to a similar size HEMT device with conventional field plate (CFP) structure, the AFP not only minimizes the parasitic gate to source capacitance, but also exhibits higher OFF-state breakdown voltage and one order of magnitude lower drain leakage current. In a device with a gate to drain distance of 6 μm and a gate length of 0.8 μm, three times higher forward blocking voltage of 375 V was obtained at V_GS=-5 V. In contrast, a similar sized HEMT with CFP can only achieve a breakdown voltage no higher than 125 V using this process, regardless of device dimensions. Moreover, a temperature coefficient of 0 V/K for the breakdown voltage is observed. However, devices without field plate (no FP) and with optimized conventional field plate (CFP) exhibit breakdown voltage temperature coefficients of -0.113 V/K and -0.065 V/K, respectively.     

Experimental and numerical analyses of high voltage 4H-SiC junction barrier Schottky rectifiers with linearly graded field limiting ring

This paper describes the successful fabrication of 4H-SiC junction barrier Schottky(JBS) rectifiers with a linearly graded field limiting ring(LG-FLR). Linearly variable ring spacings for the FLR termination are applied to improve the blocking voltage by reducing the peak surface electric field at the edge termination region, which acts like a variable lateral doping profile resulting in a gradual field distribution. The experimental results demonstrate a breakdown voltage of 5 kV at the reverse leakage current density of 2 mA/cm2(about 80% of the theoretical value). Detailed numerical simulations show that the proposed termination structure provides a uniform electric field profile compared to the conventional FLR termination, which is responsible for 45% improvement in the reverse blocking voltage despite a 3.7% longer total termination length.     

Study of 4H-SiC junction barrier Schottky diode using field guard ring termination

This paper reports that the 4H-SiC Schottky barrier diode, PiN diode and junction barrier Schottky diode terminated by field guard rings are designed, fabricated and characterised. The measurements for forward and reverse characteristics have been done, and by comparison with each other, it shows that junction barrier Schottky diode has a lower reverse current density than that of the Schottky barrier diode and a higher forward drop than that of the PiN diode. High-temperature annealing is presented in this paper as well to figure out an optimised processing. The barrier height of 0.79 eV is formed with Ti in this work, the forward drop for the Schottky diode is 2.1 V, with an ideality factor of 3.2, and junction barrier Schottky diode with blocking voltage higher than 400 V was achieved by using field guard ring termination.     

Improvement of the off-state breakdown voltage with field plate and low-density drain in AlGaN/GaN high-electron mobility transistors

We present an AlGaN/GaN high-electron mobility transistor(HEMT) device with both field plate(FP) and lowdensity drain(LDD). The LDD is realized by the injection of negatively charged fluorine(F-) ions under low power in the space between the gate and the drain electrodes. With a small-size FP and a LDD length equal to only 31% of the gate-drain spacing, the device effectively modifies the electric field distribution and achieves a breakdown voltage enhancement up to two times when compared with a device with only FP.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

Recessed-gate quasi-enhancement-mode AlGaN/GaN high electron mobility transistors with oxygen plasma treatment

In this paper,the enhancement-mode AlGaN/GaN HEMT combined with the low damage recessed-gate etching and the optimized oxygen plasma treatment was fabricated.Scanning electron microscope/energy dispersive spectrometer(SEM/EDS) method and x-ray photoelectron spectroscopy(XPS) method were used to confirm the formation of oxides.Based on the experimental results,the obtained enhancement-mode HEMT exhibited a threshold voltage of 0.5 V,a high peak transconductance of 210 mS/mm,and a maximum drain current of 610 mA/mm at the gate bias of 4 V.Meanwhile,the on/off current ratio of enhancement-mode HEMT was as high as 10~8,drain induced barrier lowering(DIBL) was as low as 5 raV/V,and subthreshold swing(SS) of 80 mV/decade was obtained.Compared with the conventional HEMT,the Schottky reverse current of enhancement-mode HEMT was three orders of magnitude lower,and the off-state breakdown voltage of which was higher.In addition,a power gain cutoff frequency(/max) of the enhancement-mode HEMT was larger than that of the conventional one.     

Influence of Schottky drain contacts on the strained AlGaN barrier layer of AlGaN/AlN/GaN heterostructure field-effect transistors

Rectangular Schottky drain AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) with different gate contact areas and conventional AlGaN/AlN/GaN HFETs as control were both fabricated with same size. It was found there is a significant difference between Schottky drain AlGaN/AlN/GaN HFETs and the control group both in drain series resistance and in two-dimensional electron gas (2DEG) electron mobility in the gate-drain channel. We attribute this to the different influence of Ohmic drain contacts and Schottky drain contacts on the strained AlGaN barrier layer. For conventional AlGaN/AlN/GaN HFETs, annealing drain Ohmic contacts gives rise to a strain variation in the AlGaN barrier layer between the gate contacts and the drain contacts, and results in strong polarization Coulomb field scattering in this region. In Schottky drain AlGaN/AlN/GaN HFETs, the strain in the AlGaN barrier layer is distributed more regularly.     

Schottky barrier MOSFET structure with silicide source/drain on buried metal

In this paper, we propose a novel Schottky barrier MOSFET structure, in which the silicide source/drain is designed on the buried metal (SSDOM). The source/drain region consists of two layers of silicide materials. Two Schottky barriers are formed between the silicide layers and the silicon channel. In the device design, the top barrier is lower and the bottom is higher. The lower top contact barrier is to provide higher {on-state} current, and the higher bottom contact barrier to reduce the off-state current. To achieve this, ErSi is proposed for the top silicide and CoSi₂ for the bottom in the n-channel case. The 50~nm n-channel SSDOM is thus simulated to analyse the performance of the SSDOM device. In the simulations, the top contact barrier is 0.2e~V (for ErSi) and the bottom barrier is 0.6eV (for CoSi₂. Compared with the corresponding conventional Schottky barrier MOSFET structures (CSB), the high on-state current of the SSDOM is maintained, and the off-state current is efficiently reduced. Thus, the high drive ability (1.2mA/μm at V_ds=1V, V_gs=2V) and the high I_on/I_min ratio (10⁶) are both achieved by applying the SSDOM structure.     

Performance assessment of nanoscale Schottky MOSFET as resonant tunnelling device: Non-equilibrium Green’s function formalism

A comprehensive study is performed on the electrical characteristics of Schottky barrier MOSFET (SBMOSFET) in nanoscale regime, by employing the non-equilibrium Green’s function (NEGF) approach. Quantum confinement results in the enhancement of effective Schottky barrier height (SBH). High enough Schottky barriers at the source/drain and the channel form a double barrier profile along the channel that results in the formation of resonance states. We have, for the first time, proposed a resonant tunnelling device based on SBMOSFET in which multiple resonance states are modulated by the gate voltage. Role of essential factors such as temperature, SBH, bias voltage and structural parameters on the feasibility of this device for silicon-based resonant tunnelling applications are extensively studied. Resonant tunnelling appears at low temperatures and low drain voltages and as a result negative differential resistance (NDR) is apparent in the transfer characteristic. Scaling down the gate length to 6 nm increases the peak-to-valley ratio (PVR) of the drain current. As the effective SBH reduces, the curvature of the double barrier profile is gradually diminished. Therefore, multiple resonant states are contributed to the current and consequently resonant tunnelling is smoothed out.     

Temperature and drain bias dependence of single event transient in 25-nm FinFET technology

In this paper,we investigate the temperature and drain bias dependency of single event transient(SET) in 25-nm fin field-effect-transistor(FinFET) technology in a temperature range of 0-135°C and supply voltage range of 0.4 V-1.6 V.Technology computer-aided design(TCAD) three-dimensional simulation results show that the drain current pulse duration increases from 0.6 ns to 3.4 ns when the temperature increases from 0 to 135°C.The charge collected increases from 45.5 fC to 436.9 fC and the voltage pulse width decreases from 0.54 ns to 0.18 ns when supply voltage increases from 0.4 V to 1.6 V.Furthermore,simulation results and the mechanism of temperature and bias dependency are discussed.     

Simulation research on offset field-plate used as edge termination in 4H-SiC merged PiN-Schottky diodes

A new structure of 4H--silicon carbide (SiC) merged PiN-Schottky (MPS) diodes with offset field-plate (FP) as edge termination is developed. To understand the influences of 4H--SiC MPS diodes with offset FP on the characteristics, simulations have been done by using ISE TCAD. Related factors of offset FP have been studied as well to optimise the reverse characteristics of 4H--SiC MPS diodes. The simulation results show that the device using offset FP can create a higher blocking voltage under reverse bias as compared with that using field guard rings. Besides, the offset FP does not cause any extra steps in the manufacture of MPS diodes.     

高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响

研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大,肖特基源漏(SBSD) SOI MOSFET的开态电流减小,这表明边缘感应势垒降低效应(FIBL)并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应(FIBS)是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现,源漏与栅是否对准,高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠,高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅,采用高k侧墙并结合堆叠栅结构,可以提高驱动电流.分析结果表明,来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密,从而达到改变势垒高度,调节驱动电流的目的. 关键词： k栅介质')" href="#">高k栅介质 肖特基源漏(SBSD) 边缘感应势垒屏蔽(FIBS) 绝缘衬底上的硅(SOI)     

Non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor with high breakdown voltage

A non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor(quasi-EDHEMT) with a thin barrier, high breakdown voltage and good performance of drain induced barrier lowering(DIBL)was presented. Due to the metal organic chemical vapor deposition(MOCVD) grown 9-nm undoped AlGaN barrier, the effect that the gate metal depleted the two-dimensiomal electron gas(2DEG) was greatly impressed. Therefore, the density of carriers in the channel was nearly zero. Hence, the threshold voltage was above 0 V. Quasi-E-DHEMT with 4.1-μm source-to-drain distance, 2.6-μm gate-to-drain distance, and 0.5-μm gate length showed a drain current of 260 mA/mm.The threshold voltage of this device was 0.165 V when the drain voltage was 10 V and the DIBL was 5.26 mV/V. The quasi-E-DHEMT drain leakage current at a drain voltage of 146 V and a gate voltage of-6 V was below 1 mA/mm. This indicated that the hard breakdown voltage was more than 146 V.     

场板结构AlGaN/GaN HEMT的电流崩塌机理

在不同的漏偏压下,研究了钝化和不同场板尺寸AlGaN/GaN HEMT对电流崩塌的抑制能力.实验结果表明,钝化器件对电流崩塌的抑制能力随着漏偏压的升高而显著下降;在高漏偏压下,场板的尺寸对器件抑制崩塌的能力有较大影响,而合适尺寸的场板结构在各个漏偏压下都能够很好的抑制电流崩塌.深入分析发现,场板结构不仅能够抑制虚栅的充电过程,而且提供了放电途径,有利于虚栅的放电,从而抑制电流崩塌.在此基础上,通过建立场板介质对虚栅放电的模型,解释了高漏偏压下场板的尺寸对器件抑制崩塌的能力有较大影响的原因. 关键词： AlGaN/GaN HEMT 场板 电流崩塌     

场板结构AlGaN/GaN HEMT的电流崩塌机理

在不同的漏偏压下，研究了钝化和不同场板尺寸AlGaN/GaN HEMT对电流崩塌的抑制能力.实验结果表明，钝化器件对电流崩塌的抑制能力随着漏偏压的升高而显著下降；在高漏偏压下，场板的尺寸对器件抑制崩塌的能力有较大影响，而合适尺寸的场板结构在各个漏偏压下都能够很好的抑制电流崩塌.深入分析发现，场板结构不仅能够抑制虚栅的充电过程，而且提供了放电途径，有利于虚栅的放电，从而抑制电流崩塌.在此基础上，通过建立场板介质对虚栅放电的模型，解释了高漏偏压下场板的尺寸对器件抑制崩塌的能力有较大影响的原因.     

Model and analysis of drain induced barrier lowering effect for 4H--SiC metal semiconductor field effect transistor

Based on an analytical solution of the two-dimensional Poisson equation in the subthreshold region, this paper investigates the behavior of DIBL (drain induced barrier lowering) effect for short channel 4H--SiC metal semiconductor field effect transistors (MESFETs). An accurate analytical model of threshold voltage shift for the asymmetric short channel 4H--SiC MESFET is presented and thus verified. According to the presented model, it analyses the threshold voltage for short channel device on the L/a (channel length/channel depth) ratio, drain applied voltage V_DS and channel doping concentration N_D, thus providing a good basis for the design and modelling of short channel 4H--SiC MESFETs device.     

单Halo全耗尽应变Si 绝缘硅金属氧化物半导体场效应管的阈值电压解析模型

为了改善金属氧化物半导体场效应管(MOSFET) 的短沟道效应(SCE)、 漏致势垒降低(DIBL) 效应, 提高电流的驱动能力, 提出了单Halo 全耗尽应变硅绝缘体 (SOI) MOSFET 结构, 该结构结合了应变Si, 峰值掺杂Halo结构, SOI 三者的优点. 通过求解二维泊松方程, 建立了全耗尽器件表面势和阈值电压的解析模型. 模型中分析了弛豫层中的Ge组分对表面势、表面场强和阈值电压的影响, 不同漏电压对表面势的影响, Halo 掺杂对阈值电压和DIBL的影响.结果表明, 该新结构能够抑制SCE和DIBL效应, 提高载流子的输运效率. 关键词： 应变Si 阈值电压 短沟道效应 漏致势垒降低