Non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor with high breakdown voltage

A non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor(quasi-EDHEMT) with a thin barrier, high breakdown voltage and good performance of drain induced barrier lowering(DIBL)was presented. Due to the metal organic chemical vapor deposition(MOCVD) grown 9-nm undoped AlGaN barrier, the effect that the gate metal depleted the two-dimensiomal electron gas(2DEG) was greatly impressed. Therefore, the density of carriers in the channel was nearly zero. Hence, the threshold voltage was above 0 V. Quasi-E-DHEMT with 4.1-μm source-to-drain distance, 2.6-μm gate-to-drain distance, and 0.5-μm gate length showed a drain current of 260 mA/mm.The threshold voltage of this device was 0.165 V when the drain voltage was 10 V and the DIBL was 5.26 mV/V. The quasi-E-DHEMT drain leakage current at a drain voltage of 146 V and a gate voltage of-6 V was below 1 mA/mm. This indicated that the hard breakdown voltage was more than 146 V.     

AlGaN/GaN HEMTs on 4-Inch Silicon Substrates in the Presence of 2.7-μm -Thick Epilayers with the Maximum Off-State Breakdown Voltage of 500 V

We report on the high breakdown performance of AlGaN/GaN high electron mobility transistors （HEMTs） grown on 4-inch silicon substrates. The HEMT structure including three Al-content step-graded AlGaN transition layers has a total thickness of 2.7 μm. The HEMT with a gate width WG of 300 μm acquires a maximum off-state breakdown voltage （BV） of 550 V and a maximum drain current of 527 mA/mm at a gate voltage of 2 V. It is found that BV is improved with the increase of gate-drain distance LGD until it exceeds 8 μm and then BV is tended to saturation. While the maximum drain current drops continuously with the increase of LGD. The HEMT with a WG of 3 mm and a LGD of 8 μm obtains an off-state BV of 500 V. Its maximum leakage current is just 13 μA when the drain voltage is below 400 V. The device exhibits a maximum output current of 1 A with a maximum transconductance of 242 mS.     

Enhancement-mode A1GaN/GaN high electronic mobility transistors with thin barrier＊

An enhancement-mode （E-mode） A1GaN/GaN high electron mobility transistor （HEMTs） was fabricated with 15-nm A1GaN barrier layer. E-mode operation was achieved by using fluorine plasma treatment and post-gate rapid thermal annealing. The thin barrier depletion-HEMTs with a threshold voltage typically around -1.7 V, which is higher than that of the 22-nm barrier depletion-mode HEMTs （-3.5 V）. Therefore, the thin barrier is emerging as an excellent candidate to realize the enhancement-mode operation. With 0.6-tim gate length, the devices treated by fluorine plasma for 150-W RF power at 150 s exhibited a threshold voltage of 1.3 V. The maximum drain current and maximum transconductance are 300 mA/mm, and 177 mS/ram, respectively. Compared with the 22-nm barrier E-mode devices, VT of the thin barrier HEMTs is much more stable under the gate step-stress,     

Breakdown mechanisms in AlGaN/GaN high electron mobility transistors with different GaN channel thickness values

In this paper,the off-state breakdown characteristics of two different AlGaN/GaN high electron mobility transistors（HEMTs）,featuring a 50-nm and a 150-nm GaN thick channel layer,respectively,are compared.The HEMT with a thick channel exhibits a little larger pinch-off drain current but significantly enhanced off-state breakdown voltage(SV_off).Device simulation indicates that thickening the channel increases the drain-induced barrier lowering（DIBL） but reduces the lateral electric field in the channel and buffer underneath the gate.The increase of BV_off in the thick channel device is due to the reduction of the electric field.These results demonstrate that it is necessary to select an appropriate channel thickness to balance DIBL and BV_off in AlGaN/GaN HEMTs.     

Performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors

We report on the performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors （MOSHEMTs） and InA1N/GaN high electron mobility transistors （HEMTs）. The MOSHEMT presents a maximum drain current of 961 mA/mm at Vgs = 4 V and a maximum transconductance of 130 mS/mm compared with 710 mA/mm at Vgs = 1 V and 131 mS/mm for the HEMT device, while the gate leakage current in the reverse direction could be reduced by four orders of magnitude. Compared with the HEMT device of a similar geometry, MOSHEMT presents a large gate voltage swing and negligible current collapse.     

An AlGaN/GaN HEMT with enhanced breakdown and a near-zero breakdown voltage temperature coefficient

An AlGaN/GaN high-electron mobility transistor(HEMT) with a novel source-connected air-bridge field plate(AFP) is experimentally verified.The device features a metal field plate that jumps from the source over the gate region and lands between the gate and drain.When compared to a similar size HEMT device with a conventional field plate(CFP) structure,the AFP not only minimizes the parasitic gate to source capacitance,but also exhibits higher OFF-state breakdown voltage and one order of magnitude lower drain leakage current.In a device with a gate to drain distance of 6 μm and a gate length of 0.8 μm,three times higher forward blocking voltage of 375 V was obtained at VGS =-5 V.In contrast,a similar sized HEMT with a CFP can only achieve a breakdown voltage no higher than 125 V using this process,regardless of device dimensions.Moreover,a temperature coefficient of 0 V/K for the breakdown voltage is observed.However,devices without a field plate(no FP) and with an optimized conventional field plate(CFP) exhibit breakdown voltage temperature coefficients of-0.113 V/K and-0.065 V/K,respectively.     

Simulation and Experimentation for Low Density Drain AlGaN/GaN HEMT

In order to improve the breakdown voltage of AlGaN/GaN high electron mobility transistors （HEMTs）, we report a feasible method of low density drain （LDD） HEMT. The fluoride-based plasma treatment using CF4 gas is performed on the drain-side of the gate edge. The channel two-dimensional electron gas （2DEG） concentrations are modulated by fluoride plasma treatment, and the peak electric field at the gate edge is effectively reduced, so the breakdown voltage is improved. The electric field distributions of the LDD-HEMTs are simulated using the Silvaco software, and the peak of the electric field on the gate edge is effectively reduced. Experimental results show that, compared with the conventional HEMT, LDD-HEMTs have a lower reverse leakage current of the gate, and the breakdown voltage is increased by 36%. The current collapse characteristics of the LDD-HEMTs are confirmed by dual-pulse measurement, and an obvious pulse current reduction is due to the surface states by implanting F ions between the gate and the drain.     

Improved breakdown voltage of AlGaN/GaN HEMTs grown on Si substrates using partially Mg-doped GaN buffer layer by MOCVD

AlGaN/GaN high electron mobility transistors(HEMTs) were grown on Si substrates by MOCVD.In the HEMT structure,a 1 μm GaN buffer layer was partially doped with Mg in an attempt to increase the resistivity and minimize the buffer leakage.The AlGaN/GaN HEMTs grown on undoped and partially Mg-doped GaN buffer layers were processed and the DC characteristics of the devices were characterized for comparing the effect of Mg doping.For the device with the partially Mg-doped GaN buffer layer,a lower drain leakage current density of 55.8 nA/mm,a lower gate leakage current density of 2.73 μA/mm,and a higher off-state breakdown voltage of 104 V were achieved with device dimensions Lg/Wg/Lgs/Lgd=1/10/1/1 μm,better than the device with the undoped GaN buffer layer,which has a higher drain leakage current density of 9.2 μA/mm,a higher gate leakage current density of 91.8 μA/mm,and a lower off-state breakdown voltage of 87 V with the same device dimensions.     

Effects of notch structures on DC and RF performances of AlGaN/GaN high electron mobility transistors

The effects of various notch structures on direct current(DC) and radio frequency(RF) performances of AlGaN/GaN high electron mobility transistors(HEMTs) are analyzed.The AlGaN/GaN HEMTs,each with a 0.8-μm gate length,50-μm gate width,and 3-μm source-drain distance in various notch structures at the AlGaN/GaN barrier layer,are manufactured to achieve the desired DC and RF characteristics.The maximum drain current(I_(ds,max)),pinch-off voltage(V_(th)),maximum transconductance(g_m),gate voltage swing(GVS),subthreshold current,gate leakage current,pulsed I-V characteristics,breakdown voltage,cut-off frequency(f_T),and maximum oscillation frequency(f_(max)) are investigated.The results show that the double-notch structure HEMT has a 30% improvement of gate voltage swing,a 42.2% improvement of breakdown voltage,and a 9% improvement of cut-off frequency compared with the conventional HEMT.The notch structure also has a good suppression of the current collapse.     

Performance of La2O3/InAlN/GaN metal—oxide—semiconductor high electron mobility transistors

We report on the performance of La2O3/InAlN/GaN metal-oxide-semiconductor high electron mobility transistors(MOSHEMTs) and InAlN/GaN high electron mobility transistors(HEMTs).The MOSHEMT presents a maximum drain current of 961 mA/mm at Vgs = 4 V and a maximum transconductance of 130 mS/mm compared with 710 mA/mm at Vgs = 1 V and 131 mS/mm for the HEMT device,while the gate leakage current in the reverse direction could be reduced by four orders of magnitude.Compared with the HEMT device of a similar geometry,MOSHEMT presents a large gate voltage swing and negligible current collapse.     

A novel 4H-SiC lateral bipolar junction transistor structure with high voltage and high current gain

In this paper, a novel structure of a 4H-SiC lateral bipolar junction transistor (LBJT) with a base field plate and double RESURF in the drift region is presented. Collector-base junction depletion extension in the base region is restricted by the base field plate. Thin base as well as low base doping of the LBJT therefore can be achieved under the condition of avalanche breakdown. Simulation results show that thin base of 0.32 μm and base doping of 3×1017 cm-3 are obtained, and corresponding current gain is as high as 247 with avalanche breakdown voltage of 3309 V when the drift region length is 30 μm. Besides, an investigation of a 4H-SiC vertical BJT (VBJT) with comparable breakdown voltage (3357 V) shows that the minimum base width of 0.25 μm and base doping as high as 8×1017 cm-3 contribute to a maximum current gain of only 128.     

Partial-SOI high voltage laterally double-diffused MOS with a partially buried n~+-layer

A novel partial silicon-on-insulator laterally double-diffused metal-oxide-semiconductor transistor （PSOI LDMOS） with a thin buried oxide layer is proposed in this paper. The key structure feature of the device is an n＋-layer, which is partially buried on the bottom interface of the top silicon layer （PBNL PSOI LDMOS）. The undepleted interface n＋-layer leads to plenty of positive charges accumulated on the interface, which will modulate the distributions of the lateral and vertical electric fields for the device, resulting in a high breakdown voltage （BV）. With the same thickness values of the top silicon layer （10 p.m） and buried oxide layer （0.375 μm）, the BV of the PBNL PSOI LDMOS increases to 432 V from 285 V of the conventional PSOI LDMOS, which is improved by 51.6%.     

A low specific on-resistance SOI LDMOS with a novel junction field plate

A low specific on-resistance SO1 LDMOS with a novel junction field plate （JFP） is proposed and investigated theo- retically. The most significant feature of the JFP LDMOS is a PP-N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buffed oxide layer （BOX） and thus widens the vertical conduction area. As a result, the breakdown voltage （BV） is improved and the specific on-resistance （Ron,sp） is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ.cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.     

Field plate structural optimization for enhancing the power gain of GaN-based HEMTs

A novel source-connected field plate structure, featuring the same photolithography mask as the gate electrode, is proposed as an improvement over the conventional field plate (FP) techniques to enhance the frequency performance in GaN-based HEMTs. The influences of the field plate on frequency and breakdown performance are investigated simultaneously by using a two-dimensional physics-based simulation. Compared with the conventional T-gate structures with a field plate length of 1.2 μm, this field plate structure can induce the small signal power gain at 10 GHz to increase by 5-9.5 dB, which depends on the distance between source FP and dramatically shortened gate FP. This technique minimizes the parasitic capacitances, especially the gate-to-drain capacitance, showing a substantial potential for millimeter-wave, high power applications.     

Novel high-voltage self-adaptive power device based on interface charge＊

This paper presents a novel high-voltage lateral double diffused metal-oxide semiconductor （LDMOS） with self- adaptive interface charge （SAC） layer and its physical model of the vertical interface electric field. The SAC can be self-adaptive to collect high concentration dynamic inversion holes, which effectively enhance the electric field of dielectric buried layer （EI） and increase breakdown voltage （BV）. The BV and EI of SAC LDMOS increase to 612 V and 600 V/tim from 204 V and 90.7 V/ttm of the conventional silicon-on-insulator, respectively. Moreover, enhancement factors of r/which present the enhanced ability of interface charge on EI are defined and analysed.     

A prototype of a high rating MRPC

Six-gap resistive plate chamber （MRPC） prototypes with semiconductive glass electrodes （bulk resistivity ～ 10^10Ω·cm） were studied for suitability in time-of-flight （TOF） applications at high rates. These studies were performed using a continuous electron beam of 800 MeV at IHEP and an X-ray machine. Time resolutions of about 100 ps and efficiencies larger than 90% were obtained for flux densities up to 28 kHz/cm^2.     

Synthesis of large diamond crystals containing high-nitrogen concentration at high pressure and high temperature using Ni-based solvent by temperature gradient method

This paper reprots that with Ni-based catalyst/solvent and with a dopant of NaN 3,large green single crystal diamonds with perfect shape are successfully synthesized by temperature gradient method under high pressure and high temperature in a China-type cubic anvil high-pressure apparatus (SPD-6×1200),and the highest nitrogen concentration reaches approximately 1214-1257 ppm calculated by infrared absorption spectra.The synthesis conditions are about 5.5 GPa and 1240-1300 C.The growth behaviour of diamond with high-nitrogen concentration is investigated in detail.The results show that,with increasing the content of NaN 3 added in synthesis system,the width of synthesis temperature region for growth high-quality diamonds becomes narrower,and the morphology of diamond crystal is changed from cube-octahedral to octahedral at same temperature and pressure,the crystal growth rate is slowed down,nevertheless,the nitrogen concentration doped in synthetic diamond increases.     

Thermal analysis for the high duty cycle PIMS accelerator

To develop the high power proton linear accelerator for the Accelerator Driven System（ADS） program,the preliminary design of the Pi mode accelerating structure（PIMS） has been carried out.It is estimated that PIMS would heat up to 80 for low duty cycle（0.1%） without water-cooling,which is not acceptable thus water-cooling is demanded.The structure stability for the high duty cycle or even for CW operation is crucially important for the ADS application.Therefore,thermal analysis with water-cooling for a high duty accelerator in our ADS research is performed to control the frequency shift caused by a temperature rise.     

Mode control in a high gain relativistic klystron amplifier with 3 GW output power

Higher mode excitation is very serious in the relativistic klystron amplifier, especially for the high gain relativistic amplifier working at tens of kilo-amperes. The mechanism of higher mode excitation is explored in the FIC simulation and it is shown that insufficient separation of adjacent cavities is the main cause of higher mode excitation. So RF lossy material mounted on the drift tube wall is adopted to suppress higher mode excitation. A high gain S-band relativistic klystron amplifier is designed for the beam current of 13 kA and the voltage of 1 MV. PIC simulation shows that the output power is 3.2 GW when the input power is only 2.8 kW.     

Low on-resistance high-voltage lateral double-diffused metal oxide semiconductor with a buried improved super-junction layer

A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.