基于Au/TiO_2/FTO结构忆阻器的开关特性与机理研究

采用简单的一步水热法在FTO导电玻璃上外延生长了锐钛矿TiO_2纳米线,制备了具有Au/TiO_2/FTO器件结构的锐钛矿TiO_2纳米线忆阻器,系统研究了器件的阻变开关特性和开关机理.结果表明,Au/TiO_2/FTO忆阻器具有非易失的双极性阻变开关特性.同时,在103s的时间内,器件在0.1 V的电阻开关比始终保持在20以上,表明器件具有良好的非易失性.此外,器件在低阻态时遵循欧姆导电特性,而在高阻态时则满足陷阱控制的空间电荷限制电流传导机制,同时提出了基于氧空位导电细丝形成与断开机制的阻变开关模型.研究结果表明Au/TiO_2/FTO忆阻器将是一种很有发展潜力的下一代非易失性存储器.     

横截面积参数对钛氧化物忆阻器导电特性的影响

纳米钛氧化物忆阻器的导电过程因自身参数的改变及不同机理的共存而呈现复杂特性,但现有研究缺乏针对横截面积参数的改变对忆阻器导电特性影响的讨论.基于杂质漂移及隧道势垒机理,本文分析了忆阻器导电过程,研究了横截面积参数与导电过程中各关键物理要素间的关联,并基于此,分别研究了钛氧化物横截面积及隧道势垒横截面积的改变对忆阻器导电特性的影响,分析了两者的区别与联系.验证了两种机理共存情况下,相对于钛氧化物横截面积的改变,隧道势垒横截面积的改变是引发忆阻器导电特性变化的主要因素,且是导致忆阻器非理想导电特性的可能因素.研究成果有助于进一步解释忆阻器导电过程的复杂性,并为优化忆阻器模型的构建提供依据.     

下电极对ZnO薄膜电阻开关特性的影响

本文采用直流磁控溅射法在三种不同的下电极(BEs)上制备了ZnO薄膜, 获得了W/ZnO/BEs存储器结构. 研究了不同的下电极材料对器件电阻开关特性的影响. 研究结果表明, 以不同下电极所制备的器件都具有单极性电阻开关特性. 在低阻态时, ZnO薄膜的导电机理为欧姆传导, 而高阻态时薄膜的导电机理为空间电荷限制电流. 不同下电极与ZnO薄膜之间的肖特基势垒高度对电阻开关过程中的操作电压有较大的影响, 并基于导电细丝模型对不同下电极上ZnO薄膜的低阻态阻值及reset电流的变化进行了解释. 关键词： ZnO薄膜 电阻开关 下电极     

具有感觉记忆的忆阻器模型

人类记忆的形成包括感觉记忆、短期记忆、长期记忆三个阶段,类似的记忆形成过程在不同材料忆阻器的实验研究中有过多次报道.这类忆阻器的记忆形成过程存在有、无感觉记忆的两种情况,已报道的这类忆阻器的数学模型仅能够描述无感觉记忆的忆阻器.本文在已有模型的基础上,根据有感觉记忆的忆阻器的研究文献中所报道的实验现象,设计了具有感觉记忆的忆阻器模型.对所设计模型的仿真分析验证了该模型对于存在感觉记忆的这类忆阻器特性的描述能力:对忆阻器施加连续脉冲激励,在初始若干脉冲作用时忆阻器无明显的记忆形成,此时忆阻器处于感觉记忆阶段,后续的脉冲作用下忆阻器将逐渐形成短期、长期记忆,并且所施加脉冲的幅值越大、宽度越大、间隔越小,则感觉记忆阶段所经历的脉冲数量越少.模型状态变量的物理意义可用连通两电极的导电通道在外加电压作用下的形成与消失来给出解释.     

忆阻器、忆容器和忆感器的Simulink建模及其特性分析

忆阻器、忆容器和忆感器均是具有记忆特性的新型非线性电路元件,也被称为记忆元件.以三种电路元件的通用数学模型为依据,从数学分析的角度,对忆阻器、忆容器和忆感器的Simulink模型进行了建立.在Simulink模型中体现了记忆元件对历史状态和系统状态变量的依赖性,正确表现出其独特的记忆特性.通过一系列仿真分析,得到了忆阻器、忆容器和忆感器的元件特性,验证了模型的有效性.此外,通过对三者在不同参数、不同激励下的电路特性分析,得到了三种记忆元件等效模型随频率和幅值变化的规律,为以后忆阻器、忆容器和忆感器基于Simulink的仿真研究和应用研究奠定基础.     

具有经验学习特性的忆阻器模型分析

类似人类记忆的短期、长期记忆现象在不同材料忆阻器的实验研究中有过多次报道.在多篇这类忆阻器的研究文献中还报道了经验学习特性:"学习-遗忘-再学习"实验中,短期记忆遗忘后再次学习,记忆恢复的速度明显比初次学习的记忆形成速度更快.本文对这类忆阻器已有数学模型在"学习-遗忘-再学习"实验中的特性给出进一步分析.仅考虑短期、长期记忆现象的忆阻模型在该实验中表现为较快速再次学习特性,再次学习的记忆恢复速度较快主要是由于脉冲间隔期间的遗忘速度比初次学习时更慢.考虑经验学习特性的忆阻模型在再学习阶段的记忆恢复速度更快主要是因为脉冲作用时的记忆增速更快,同时仍然存在脉冲间隔期间的遗忘速度减慢.与经验学习特性相关的状态变量的物理意义可利用连通两电极的导电通道的周围区域在不同外加电压作用下的变化来给出解释.     

基于串并联磁控忆阻器的耦合行为研究

忆阻器是纳米级器件, 其功耗低, 集成度高, 有着巨大的应用潜能. 单个器件具有丰富的电学性质, 其串并联电路更展现了丰富的动力学行为. 然而, 忆阻器在高密度集成的环境下, 其耦合效应不可忽视. 因此, 本文首先基于磁控忆阻器推导了耦合忆阻器的数学模型. 其次, 在考虑不同极性连接和耦合强度的前提下, 讨论两个磁控忆阻器串并联的耦合情况, 进行了详细的理论分析, 并通过数值仿真探索了耦合效应对忆阻系统的影响. 同时, 设计了基于Matlab的图形用户界面, 直观地展示了不同参数下的耦合特性曲线. 进一步, 本文展示了有无耦合情况下, 初始阻值对忆阻器正常工作范围的影响. 最后, 构建耦合忆阻器的Pspice仿真器, 从电路的角度再次验证了忆阻器间的耦合效应. 实验结果表明: 同极性耦合增强了阻值的改变, 相反极性的耦合减缓了阻值的改变. 这些动力学特性可以很好地应用于忆阻网络中, 也为全面考虑忆阻系统电路的设计提供了强大的理论基础.     

忆阻器研究新进展:基于二维材料的可耐受超高温忆阻器

正忆阻器是一种由两个端子和一个导电通道组成的电子元件,其电阻可以通过施加的电压或电流操作进行调节。因此,该器件是一种具有"记忆"能力的电阻,并可应用于存储和类脑计算等领域。华裔科学家蔡少棠在1971年首先提出了忆阻器的概念。他指出除了电阻器、电感器和电容器之外,还应该存在第四种基本电路元件,即忆阻器[1]。2008年,惠普实验室首次从实验上建立了忆阻器的概念与固态电子器件的联系[2],证实     

钙钛矿相界面插层对SrFeOx基忆阻器的性能提升

SrFeO_x(SFO)是一种能在SrFeO_2.5钙铁石(BM)相和SrFeO₃钙钛矿(PV)相之间发生可逆拓扑相变的材料.这种相变能显著改变电导却维持晶格框架不变,使SFO成为一种可靠的阻变材料.目前大部分SFO基忆阻器使用单层BM-SFO作为阻变功能层,这种器件一般表现出突变型阻变行为,因而其应用被局限于两态存储.对于神经形态计算等应用,单层BM-SFO忆阻器存在阻态数少、阻值波动大等问题.为解决这些问题,本研究设计出BM-SFO/PV-SFO双层忆阻器,其中PV-SFO层为富氧界面插层,可在导电细丝形成过程中提供大量氧离子并在断裂过程中回收氧离子,使导电细丝的几何尺寸(如直径)在更大范围内可调,从而获得更多、更连续且稳定的阻态,可用于模拟长时程增强和抑制等突触行为.基于该器件仿真构建了全连接神经网络(ANN),在手写体数字光学识别(ORHD)数据集进行在线训练后获得了86.3%的识别准确率,相比于单层忆阻器基ANN的准确率提升69.3%.本研究为SFO基忆阻器性能调控提供了一种新方法,并展示了它们作为人工突触器件在神...     

基于模拟电路的新型忆感器等效模型

本文首先利用光敏电阻阻值的可控性, 建立了磁通控制型忆阻器的等效电路模型. 通过对忆感器和忆阻器间转换关系的分析, 采用模拟电子元器件设计了磁通控制型忆感器的实用等效电路模型, 给出了理论分析并结合Pspice软件进行了仿真验证. 忆感器等效电路模型的韦安关系展现出典型的非线性磁滞回线特性. 最后, 运用实验手段研究了正弦波和三角波两种典型电压信号激励下忆感器与RC串联后电路的动态特征, 证明了本文提出忆感器等效电路模型的有效性. 关键词： 忆阻器 忆感器 磁滞回线特性 Pspice     

Ti/HfO2/Pt阻变存储单元中的氧空位聚簇分布

为了研究阻变存储器导电细丝的形成位置和分布规律, 使用X射线光电子能谱研究了Ti/HfO₂/Pt阻变存储器件单元中Hf 4f的空间分布, 得到了阻变层的微结构信息. 通过I-V测试, 得到该器件单元具有典型的阻变特性; 通过针对Hf 4f的不同深度测试, 发现处于低阻态时, 随着深度的增加, Hf⁴⁺化学组分单调地减小; 而处于高阻态和未施加电压前, 该组分呈现波动分布; 通过Hf⁴⁺在高阻态和低阻态下组分含量以及电子能损失谱分析, 得到高阻态下Hf⁴⁺组分的平均含量要高于低阻态; 另外, 高阻态和低阻态下的O 1s谱随深度的演变也验证了Hf⁴⁺的变化规律. 根据实验结果, 提出了局域分布的氧空位聚簇可能是造成这一现象的原因. 空位簇间的链接和断裂决定了导电细丝的形成和消失. 由于导电细丝容易在氧空位缺陷聚簇的地方首先形成, 这一研究为导电细丝的发生位置提供了参考.     

SPICE modeling of memristors with multilevel resistance states

With CMOS technologies approaching the scaling ceiling, novel memory technologies have thrived in recent years, among which the memristor is a rather promising candidate for future resistive memory (RRAM). Memristor’s potential to store multiple bits of information as different resistance levels allows its application in multilevel cell (MCL) technology, which can significantly increase the memory capacity. However, most existing memristor models are built for binary or continuous memristance switching. In this paper, we propose the simulation program with integrated circuits emphasis (SPICE) modeling of charge-controlled and flux-controlled memristors with multilevel resistance states based on the memristance versus state map. In our model, the memristance switches abruptly between neighboring resistance states. The proposed model allows users to easily set the number of the resistance levels as parameters, and provides the predictability of resistance switching time if the input current/voltage waveform is given. The functionality of our models has been validated in HSPICE. The models can be used in multilevel RRAM modeling as well as in artificial neural network simulations.     

Analysis and modeling of resistive switching mechanism oriented to fault tolerance of resistive memory based on memristor

With the progress of the semiconductor industry, resistive memories, especially the memristor, have drawn increasing attention. The resistive memory based on memrsitor has not been commercialized mainly because of data error. Currently, there are more studies focused on fault tolerance of resistive memory. This paper studies the resistive switching mechanism which may have time-varying characteristics. Resistive switching mechanism is analyzed and its respective circuit model is established based on the memristor Spice model.     

Bipolar resistive switching in BiFe_(0.95)Zn_(0.05)O_3 films

Bipolar resistive switching is studied in BiFe0.95Zn0.05O3 films prepared by pulsed laser deposition on （001） SrTiO3 substrate, with LaNiO3 as the bottom electrode, and Pt as the top electrode. Multiple steps of resistance change are ob- served in the resistive switching process with a slow voltage sweep, indicating the formation/rupture of multiple conductive filaments. A resistive ratio of the high resistance state （HRS） to the low resistance state （LRS） of over three orders of mag- nitude is observed. Furthermore, the conduction mechanism is confirmed to be space-charge-limited conduction with the Schottky emission at the interface with the top Pt electrodes in the HRS, and Ohmic in the LRS. Impedance spectroscopy demonstrates a conductive ferroelectric/interfacial dielectric 2-layer structure, and the formation/rupture of the conductive filaments mainly occurs at the interfacial dielectric layer close to the top Pt electrodes.     

Role of an oxide interface in a resistive switch

In the present era of data-driven architectures like 5G, Internet of things (IoT), Artificial Intelligence (AI), etc, the requirement of fast-switchable memory storage is more than ever. Oxide resistive switches are considered to be a primary choice in the non-volatile memory design. In this work, we have engineered the conventional metal-insulator-metal (MIM) structure of an oxide memristor (Ag/ZnO/ITO) by inducing an additional oxide layer La_0.7Sr_0.3MnO₃ (LSMO) at the interface between the active layer (ZnO) and Ag electrode. The presence of LSMO acts as a reservoir for the oxygen vacancies, easing the conducting filament formation process in ZnO, thereby enabling drastic improvement of the switching performance and offering reliable endurance over multiple switching cycles. First-principles-based calculations suggested the role of oxygen vacancies in controlling the electronic state of ZnO and formation of vacancies in the resistive switching process, which is in agreement with the experimental observation. The current results pave ways for improving the switching performance of resistive memory circuits through simple structural engineering incorporation, which lies at the heart of oxide electronics.     

Analysis and modeling of resistive switching mechanisms oriented to resistive random-access memory

With the progress of the semiconductor industry,the resistive random-access memory(RAM) has drawn increasing attention.The discovery of the memristor has brought much attention to this study.Research has focused on the resistive switching characteristics of different materials and the analysis of resistive switching mechanisms.We discuss the resistive switching mechanisms of different materials in this paper and analyze the differences of those mechanisms from the view point of circuitry to establish their respective circuit models.Finally,simulations are presented.We give the prospect of using different materials in resistive RAM on account of their resistive switching mechanisms,which are applied to explain their resistive switchings.     

Dynamic resistive switching in a three-terminal device based on phase separated manganites

A three-terminal device based on electronic phase separated manganites is suggested to produce high performance resistive switching. Our Monte Carlo simulations reveal that the conductive filaments can be formed/annihilated by reshaping the ferromagnetic metal phase domains with two cross-oriented switching voltages. Besides, by controlling the high resistance state(HRS) to a stable state that just after the filament is ruptured, the resistive switching remains stable and reversible, while the switching voltage and the switching time can be greatly reduced.     

Resistive switching behaviors of Cu/TaOx/TiN device with combined oxygen vacancy/copper conductive filaments

Forming-free and self-compliant bipolar resistive switching is observed in Cu/TaO_x/TiN conductive bridge random access memory. Generally, Pt has been investigated as an inert electrode. However, Pt is not desirable material in current semiconductor industry for mass production. In this study, all electrodes are adapted to complementary metal-oxide-semiconductor compatible materials. The self-compliant resistive switching is achieved via usage of TiN bottom electrode. Also, dissolved Cu ions in TaO_x lead to forming-free resistive switching behavior. The resistive switching mechanism is formation and rupture of combined oxygen vacancy/metallic copper conductive filament. We propose that Cu/TaO_x/TiN is a promising candidate for a conductive bridge random access memory structure.