双电层氧化锌薄膜晶体管偏压应力稳定性

以环保可降解的天然生物材料制备功能器件越来越受到关注,利用天然鸡蛋清作为栅介质层,采用射频磁控溅射法在其上沉积ZnO薄膜有源层,制备低压双电层氧化锌基薄膜晶体管（ZnO-TFT）并对其电学特性进行了表征,研究了器件在栅偏压和漏偏压应力下电性能的稳定性及其内在的物理机制。该ZnO-TFT器件呈现出良好的电特性,载流子饱和迁移率为5.99 cm²/（V·s）,阈值电压为2.18 V,亚阈值摆幅为0.57 V/dec,开关电流比为1.2×10⁵,工作电压低至3 V。研究表明,在偏压应力作用下,该ZnO-TFT器件电性能存在一定的不稳定性,我们认为栅偏压应力引起的电性能变化可能来源于栅介质附近及界面处的正电荷聚集、充放电效应和新陷阱态的复合效应;漏偏压应力引起的电性能变化可能来源于焦耳热引起的氧空位及沟道中的电子陷阱。     

γ射线总剂量辐照效应对应变Si p型金属氧化物半导体场效应晶体管阈值电压与跨导的影响研究

分析了双轴应变Si p型金属氧化物半导体场效应晶体管(PMOSFET)在γ射线辐照下载流子的微观输运过程,揭示了γ射线的作用机理及器件电学特性随辐照总剂量的演化规律,建立了总剂量辐照条件下的双轴应变Si PMOSFET阈值电压与跨导等电学特性模型,并对其进行了模拟仿真.由仿真结果可知,阈值电压的绝对值会随着辐照总剂量的积累而增加,辐照总剂量较低时阈值电压的变化与总剂量基本呈线性关系,高剂量时趋于饱和;辐照产生的陷阱电荷增加了沟道区载流子之间的碰撞概率,导致了沟道载流子迁移率的退化以及跨导的降低.在此基础上,进行实验验证,测试结果表明实验数据与仿真结果基本相符,为双轴应变Si PMOSFET辐照可靠性的研究和应变集成电路的应用与推广提供了理论依据和实践基础.     

$lt;i$gt;γ$lt;/i$gt;射线总剂量辐照效应对应变Sip型金属氧化物半导体场效应晶体管阈值电压与跨导的影响研究

分析了双轴应变Si p型金属氧化物半导体场效应晶体管(PMOSFET)在γ射线辐照下载流子的微观输运过程, 揭示了γ射线的作用机理及器件电学特性随辐照总剂量的演化规律, 建立了总剂量辐照条件下的双轴应变Si PMOSFET 阈值电压与跨导等电学特性模型, 并对其进行了模拟仿真. 由仿真结果可知, 阈值电压的绝对值会随着辐照总剂量的积累而增加, 辐照总剂量较低时阈值电压的变化与总剂量基本呈线性关系, 高剂量时趋于饱和; 辐照产生的陷阱电荷增加了沟道区载流子之间的碰撞概率, 导致了沟道载流子迁移率的退化以及跨导的降低. 在此基础上, 进行实验验证, 测试结果表明实验数据与仿真结果基本相符, 为双轴应变Si PMOSFET辐照可靠性的研究和应变集成电路的应用与推广提供了理论依据和实践基础. 关键词： 应变Sip型金属氧化物半导体场效应晶体管 总剂量辐照 阈值电压 跨导     

SiC肖特基源漏MOSFET的阈值电压

SiC肖特基源漏MOSFET的阈值电压不同于传统的MOSFET的阈值电压.在深入分析工作机理的基础上,利用二维模拟软件ISE提取并分析了器件的阈值电压.对SiC肖特基源漏MOSFET的阈值电压给出物理描述,得出当源极载流子主要以场发射方式进入沟道,同时沟道进入强反型状态,此时的栅电压是该器件的阈值电压. 关键词： 碳化硅 肖特基接触 阈值电压     

结构参数对N极性面GaN/InAlN高电子迁移率晶体管性能的影响

基于漂移-扩散传输模型、费米狄拉克统计模型以及Shockley-Read-Hall复合模型等,通过自洽求解薛定谔方程、泊松方程以及载流子连续性方程,模拟研究了材料结构参数对N极性面GaN/InAlN高电子迁移率晶体管性能的影响及其物理机制.结果表明,增加GaN沟道层的厚度(5—15 nm)与InAlN背势垒层的厚度(10—40 nm),均使得器件的饱和输出电流增大,阈值电压发生负向漂移.器件的跨导峰值随Ga N沟道层厚度的增加与InAlN背势垒层厚度的减小而减小.模拟中,各种性能参数的变化趋势均随GaN沟道层与InAlN背势垒层厚度的增加而逐渐变缓,当GaN沟道层厚度超过15 nm、InAlN背势垒层厚度超过40 nm后,器件的饱和输出电流、阈值电压等参数基本趋于稳定.材料结构参数对器件性能影响的主要原因可归于器件内部极化效应、能带结构以及沟道中二维电子气的变化.     

介质中双缺陷电荷对碳纳米管场效应晶体管量子输运特性的影响

用非平衡格林函数理论和紧束缚模型近似计算长沟道弹道输运p型碳纳米管场效应管中电流强度.研究当场效应管介质（SiO₂）中存在两个带电缺陷时，载流子散射所引起的电流强度减小和栅极阈值电压偏移量与缺陷位置的关系.介质中两个缺陷所带电荷Q₁=Q₂=+e（-e为电子电荷），都靠近源极或者都靠近漏极，或者一个电荷靠近源极另一个电荷靠近漏极.在工作状态下，所引起的电流强度相对减小比介质中只存在单个正电荷Q=+e且靠近源极（或漏极）时所引起的电流强度相对减小大得多.如果两个正电荷都在沟道中央附近，随着两个电荷的轴向距离减小，栅极阈值电压偏移的绝对值明显增加.栅极阈值电压偏移可达到-0.35 V.     

堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管二维模型

提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.     

沟道宽长比对深亚微米NMOSFET总剂量辐射与热载流子损伤的影响

本文对不同沟道宽长比的NMOSFET进行了辐射与热载流子应力的试验研究,电参数测量数据表明: 虽然两种损伤的原理具有相似之处,但总剂量辐射与热载流子的损伤表现形式及对沟道宽长比的依赖关系均不同.辐射损伤的最大特点是关态泄漏电流增加,并且损伤与沟道宽长比成反比;热载流子损伤会造成跨导等参数的显著变化,但关态泄漏电流无明显改变,并且损伤随沟道长度与宽度的减小而增大.从二者基本原理出发,结合宏观参数的表现形式,文中对辐射与热载流子损伤进行了详细分析,认为造成二者损伤差异及对沟道宽长比不同依赖关系的原因在于辐射与热载子注入引入的陷阱电荷部位不同.因此对两种损伤进行加固时应重点从器件设计尺寸、结构等方面综合考虑.     

双有源层结构掺硅氧化锌薄膜晶体管的电特性

为降低氧化锌薄膜晶体管(ZnO-TFT)的关态电流(I_off),提高开关电流比(I_on/I_off),采用磁控溅射法制备掺硅氧化锌薄膜晶体管(SZO-TFT)和SZO/ZnO双层有源层结构的TFT器件,研究了Si含量对SZO薄膜透光性和SZO-TFT电性能的影响,比较了单层与双层有源层结构TFT器件的电特性.与ZnO-TFT相比,SZO-TFT的I_off低2个数量级,最低达1.5×10^-12 A;I_on/I_off高两个数量级,最高达7.97×10⁶.而SZO/ZnO双有源层结构的TFT器件可在不降低载流子迁移率的情况下,I_on/I_off比ZnO-TFT提高近两个数量级,有效改善了器件的整体性能.     

纳米尺度金属-氧化物半导体场效应晶体管沟道热噪声模型

随着CMOS工艺的发展,热载流子效应对沟道热噪声的影响随着器件尺寸的降低而增大,传统热噪声模型未能准确表征沟道的热噪声.本文通过解能量平衡方程,得到电子温度表达式,并结合沟道漏电流表达式,建立了沟道热噪声模型.利用建立的电子温度表达式,该热噪声模型考虑了热载流子效应的影响,并且在计算热噪声的过程中考虑了电子温度对迁移率降低的影响以及温度梯度对热噪声的影响.通过分析与计算,结果显示,随着器件尺寸的减小,温度梯度对电子温度产生显著影响,使得热载流子效应的影响增大,热载流子效应对热噪声的增长作用超过了迁移率降低对热噪声的减小作用,最终导致热噪声增大.本文建立的沟道热噪声模型可应用于纳米尺寸金属-氧化物半导体场效应晶体管器件的噪声性能分析及建模.     

Enhanced performances of ZnO-TFT by improving surface properties of channel layer

Top-contact thin film transistors with ZnO as the channel layer and thermally grown SiO₂ as the gate dielectric were fabricated by using rf sputtering. The performances of ZnO-TFTs with different thicknesses of the active layer were investigated and the optimized condition was obtained. With the active layer thickness from 25 to 70 nm, the leakage current of devices increased from 10⁻¹⁰ to 10⁻⁸ A, and the on/off ratio decreased from 1.2×10⁷ to 2×10⁴. Atomic force microscope research indicated that with the thickness increased, the surface morphology of the active layer improved noticeably at first and then deteriorated. The 25-nm-thick ZnO TFT had the best surface morphology, and showed the best performance with a field effect mobility of 5.1 cm²/V S, on/off ratio of 1.2×10⁷ and threshold voltage of 20 V. This indicates that the surface properties of the channel layer have crucial affects on the performances of ZnO-TFTs.     

量子点浮置栅量子线沟道三栅结构单电子场效应管存储特性的数值模拟

通过建立二维薛定谔方程和泊松方程数值模型,对基于硅量子点浮置栅和硅量子线沟道三栅结构单电子场效应管(FET)存储特性进行了研究.通过在不同尺寸、栅压和不同写入电荷条件下,对硅量子线沟道中电子浓度的二维有限元自洽数值求解,研究了在纳米尺度下硅量子线沟道中量子限制效应和电荷分布对于器件特性的影响.模拟结果发现,沟道的导通阈值电压随着尺寸的缩小而提高,并随浮置栅内存储的电子数目的增加而明显升高.然而,这样的增加趋势在受到纳米尺度沟道中高电荷密度的影响下将出现非线性饱和趋势.进一步研究发现,当沟道尺寸较小时,沟道 关键词： 三栅单电子FET存储器 量子效应 薛定谔方程 泊松方程     

Bias stress effect in low-voltage organic thin-film transistors

The bias stress effect in pentacene organic thin-film transistors has been investigated. The transistors utilize a thin gate dielectric based on an organic self-assembled monolayer and thus can be operated at low voltages. The bias stress-induced threshold voltage shift has been analyzed for different drain-source voltages. By fitting the time-dependent threshold voltage shift to a stretched exponential function, both the maximum (equilibrium) threshold voltage shift and the time constant of the threshold voltage shift were determined for each drain-source voltage. It was found that both the equilibrium threshold voltage shift and the time constant decrease significantly with increasing drain-source voltage. This suggests that when a drain-source voltage is applied to the transistor during gate bias stress, the tilting of the HOMO and LUMO bands along the channel creates a pathway for the fast release of trapped carriers.     

Ta2O5绝缘层厚度对ZnO基薄膜晶体管器件性能的影响

报道了不同厚度TaO5栅绝缘层对氧化锌薄膜晶体管器件性能的影响.在室温下用射频磁控溅射分别制备了100,85,60,40 nm厚度的Ta2O5薄膜作为绝缘层的一组底栅氧化锌薄膜晶体管器件.从实验结果可以得出如下结论:随着Ta2O5栅绝缘层厚度的增加,相应器件的场效应迁移率下降,其数值分别是50.5,59.3,63.8,...     

太赫兹互补金属氧化物半导体场效应管探测器理论模型中扩散效应研究

针对基于经典动力学理论传统模型中忽略扩散效应的问题,通过对基于玻尔兹曼理论的场效应管传输线模型的理论分析,建立了包含扩散效应的太赫兹互补金属氧化物半导体(CMOS)场效应管探测器理论模型,研究扩散效应对场效应管电导及响应度的影响.同时,将此模型与忽略了扩散效应的传统模型进行了对比仿真模拟,给出了两种模型下的电流响应度随温度及频率变化的差别.依据仿真结果,并结合3σ原则明确了场效应管传输线模型中扩散部分省略的依据和条件.研究结果表明:扩散部分引起的响应度差异大小主要由场效应管的工作温度及工作频率决定.其中工作频率起主要作用,温度变化对差异大小影响较为微弱;而对于工作频率而言,当场效应管工作频率小于1 THz时,模型中的扩散部分可以忽略不计;而当工作频率大于1 THz时,扩散部分不可省略,此时场效应管模型需同时包含漂移、散射及扩散三个物理过程.本文的研究结果为太赫兹CMOS场效应管理论模型的精确建立及模拟提供了理论支持.     

AlGaN/GaN高电子迁移率器件外部边缘电容的物理模型

AlGaN/GaN HEMT外部边缘电容Cofd是由栅极垂直侧壁与二维电子气水平壁之间的电场构成的等效电容.本文基于保角映射法对Cofd进行物理建模,考虑沟道长度调制效应,研究外部偏置、阈值电压漂移和温度变化对Cofd的影响:随着漏源偏压从零开始增加,Cofd先保持不变再开始衰减,其衰减速率随栅源偏压的增加而减缓;AlGaN势垒层中施主杂质浓度的减小和Al组分的减小都可引起阈值电压的正向漂移,正向阈值漂移会加强沟道长度调制效应对Cofd的影响,导致Cofd呈线性衰减.在大漏极偏压工作情况下,Cofd对器件工作温度的变化更加敏感.     

Study on a novel vertical enhancement-mode Ga2O3 MOSFET with FINFET structure

A novel enhanced mode(E-mode)Ga₂O₃ metal-oxide-semiconductor field-effect transistor(MOSFET)with vertical FINFET structure is proposed and the characteristics of that device are numerically investigated.It is found that the concentration of the source region and the width coupled with the height of the channel mainly effect the on-state characteristics.The metal material of the gate,the oxide material,the oxide thickness,and the epitaxial layer concentration strongly affect the threshold voltage and the output currents.Enabling an E-mode MOSFET device requires a large work function gate metal and an oxide with large dielectric constant.When the output current density of the device increases,the source concentration,the thickness of the epitaxial layer,and the total width of the device need to be expanded.The threshold voltage decreases with the increase of the width of the channel area under the same gate voltage.It is indicated that a set of optimal parameters of a practical vertical enhancement-mode Ga₂O₃ MOSFET requires the epitaxial layer concentration,the channel height of the device,the thickness of the source region,and the oxide thickness of the device should be less than 5×10¹⁶ cm^-3,less than 1.5μm,between 0.1μm-0.3μm and less than 0.08μm,respectively.     

Effect of channel thickness on electrical performance of amorphous IGZO thin-film transistor with atomic layer deposited alumina oxide dielectric

We have investigated the electrical performance of amorphous indium–gallium–zinc oxide (α-IGZO) thin-film transistors with various channel thicknesses. It is observed that when the α-IGZO thickness increases, the threshold voltage decreases as reported at other researches. The intrinsic field-effect mobility as high as 11.1 cm²/Vs and sub threshold slope as low as ∼0.2 V/decade are independent on the thickness of α-IGZO channel, which indicate the excellent interface between α-IGZO and atomic layer deposited Al₂O₃ dielectric even for the case with α-IGZO thickness as thin as 10 nm. However, the source and drain series resistances increased with increasing of α-IGZO channel thickness, which results in the apparent field-effect mobility decreasing. The threshold voltage shift (ΔV_th) under negative bias stress (NBS) and negative bias illumination stress (NBIS) were investigated, also. The hump-effect in the sub threshold region under NBS and threshold voltage shift to negative position under NBIS were enhanced with decreasing of α-IGZO channel thickness, owing to the enhancement of vertical electrical field in channel.     

Degradation of gate-recessed MOS-HEMTs and conventional HEMTs under DC electrical stress

The performance degradation of gate-recessed metal–oxide–semiconductor high electron mobility transistor(MOSHEMT) is compared with that of conventional high electron mobility transistor(HEMT) under direct current(DC) stress,and the degradation mechanism is studied. Under the channel hot electron injection stress, the degradation of gate-recessed MOS-HEMT is more serious than that of conventional HEMT devices due to the combined effect of traps in the barrier layer, and that under the gate dielectric of the device. The threshold voltage of conventional HEMT shows a reduction under the gate electron injection stress, which is caused by the barrier layer traps trapping the injected electrons and releasing them into the channel. However, because of defects under gate dielectrics which can trap the electrons injected from gate and deplete part of the channel, the threshold voltage of gate-recessed MOS-HEMT first increases and then decreases as the conventional HEMT. The saturation phenomenon of threshold voltage degradation under high field stress verifies the existence of threshold voltage reduction effect caused by gate electron injection.