Suppression of bias stress-induced degradation of pentacene-TFT using MoOx interlayer

The bias stress effect in pentacene thin-film transistors (TFTs) with and without MoO_x interlayer was characterized. The device without MoO_x interlayer showed a large threshold voltage shift of 5.1 V after stressing with a constant gate-source voltage of −40 V for 10000 s, while at the same condition, the device with MoO_x interlayer showed a low threshold voltage shift of 1.9 V. The results can be attributed to the stable interface between MoO_x/pentacene and small contact resistance change for the device with MoO_x/Cu electrode. Pentacene-TFTs with MoO_x interlayer showed a high field-effect mobility of 0.61 cm²/V s and excellent bias stability, which could be a significant step toward the commercialization of OTFT technology.     

Room-temperature flexible thin film transistor with high mobility

We report a room-temperature and high-mobility InGaZnO thin-film transistor on flexible substrate. To gain both high gate capacitance and low leakage current, we adopt stacked dielectric of Y₂O₃/TiO₂/Y₂O₃. This flexible IGZO TFT shows a low threshold voltage of 0.45 V, a small sub-threshold swing of 0.16 V/decade and very high field-effect mobility of 40 cm²/V. Such good performance is mainly contributed by improved gate stack structure and thickness modulation of IGZO channel that reduce the interface trap density without apparent mobility degradation.     

Degradation and its fast recovery in a-IGZO thin-film transistors under negative gate bias stress

A new type of degradation phenomena featured with increased subthreshold swing and threshold voltage after negative gate bias stress (NBS) is observed for amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs), which can recover in a short time. After comparing with the degradation phenomena under negative bias illumination stress (NBIS), positive bias stress (PBS), and positive bias illumination stress (PBIS), degradation mechanisms under NBS is proposed to be the generation of singly charged oxygen vacancies ($V_{\mathrm{o}}^{+}$) in addition to the commonly reported doubly charged oxygen vacancies ($V_{\mathrm{o}}^{2+}$). Furthermore, the NBS degradation phenomena can only be observed when the transfer curves after NBS are measured from the negative gate bias to the positive gate bias direction due to the fast recovery of $V_{\mathrm{o}}^{+}$ under positive gate bias. The proposed degradation mechanisms are verified by TCAD simulation.     

Control of electrical properties and gate bias stress stability in solution-processed a-IZO TFTs by Zr doping

Zr-doped indium zinc oxide (IZO) thin film transistors (TFTs) are fabricated via a solution process with different Zr doping ratios. The addition of Zr suppressed the carrier concentration in the IZO films, which was confirmed by Hall Effect measurements. As the amount of Zr was increased in the oxide active layer of TFTs, the subthreshold swing (S.S) reduced, the ON/OFF ratio improved, and the threshold voltage (V_th) shifted positively. Moreover, the starting points of the ON state for TFTs near the point zero gate voltage could be controlled by the addition of Zr. The 0.3% Zr-doped IZO TFT exhibited a high saturation mobility of 7.0 cm² V⁻¹ s⁻¹, ON/OFF ratio of 2.6 × 10⁶ and S.S of 0.57 V/decade compared the IZO TFT with 10.1 cm² V⁻¹ s⁻¹, 1.7 × 10⁶ and 0.75 V/decade. The Zr effect of the gate bias stability was examined. Zr-doped IZO TFTs were relatively unstable under a positive bias stress (PBS), whereas they showed good stability at a negative bias stress (NBS). The gate bias stability of the oxide TFTs were compared with the extracted parameters through a stretched-exponential equation. The characteristic trapping time under NBS of 0.3% Zr-doped IZO TFTs was improved from 8.3 × 10⁴ s for the IZO TFT to 3.1 × 10⁵ s.     

SiOx interlayer to enhance the performance of InGaZnO-TFT with AlOx gate insulator

We have fabricated indium–gallium–zinc (IGZO) thin film transistor (TFT) using SiO_x interlayer modified aluminum oxide (AlO_x) film as the gate insulator and investigated their electrical characteristics and bias voltage stress. Compared with IGZO-TFT with AlO_x insulator, IGZO-TFT with AlO_x/SiO_x insulator shows superior performance and better bias stability. The saturation mobility increases from 5.6 cm²/V s to 7.8 cm²/V s, the threshold voltage downshifts from 9.5 V to 3.3 V, and the contact resistance reduces from 132 Ωcm to 91 Ωcm. The performance improvement is attributed to the following reasons: (1) the introduction of SiO_x interlayer improves the insulator surface properties and leads to the high quality IGZO film and low trap density of IGZO/insulator interface. (2) The better interface between the channel and S/D electrodes is favorable to reduce the contact resistance of IGZO-TFT.     

An analytical threshold voltage model for dual-strained channel PMOSFET

Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si 1-x Ge x /relaxd Si 1-y Ge y (s-Si/s-SiGe/Si 1-y Ge y) metal-oxide-semiconductor field-effect transistor (PMOSFET),an-alytical expressions of the threshold voltages for buried channel and surface channel are presented.And the maximum allowed thickness of s-Si is given,which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si),because the hole mobility in the buried channel is higher than that in the surface channel.Thus they offer a good accuracy as compared with the results of device simulator ISE.With this model,the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted,such as Ge fraction,layer thickness,and doping concentration.This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si 1-y Ge y metal-oxide-semiconductor field-effect transistor (MOSFET) designs.     

High‐mobility flexible thin‐film transistors with a low‐temperature zirconium‐doped indium oxide channel layer

Thin film transistors (TFTs) with zirconium‐doped indium oxide (ZrInO) channel layer were successfully fabricated on a flexible PEN substrate with process temperature of only 150 °C. The flexible ZrInO TFT exhibited excellent electrical performance with a saturation mobility of as high as 22.6 cm² V^–1 s^–1, a sub‐threshold swing of 0.39 V/decade and an on/off current ratio of 2.5 × 10⁷. The threshold voltage shifts were 1.89 V and ?1.56 V for the unpassivated flexible ZrInO TFT under positive and negative gate bias stress, respectively. In addition, the flexible ZrInO TFT was able to maintain the relatively stable performance at bending curvatures larger than 20 mm, but the off current increased apparently after bent at 10 mm. Detailed studies showed that Zr had an effect of suppress the free carrier generation without seriously distorting the In₂O₃ lattice. (© 2016 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Improving the electrical performance of HfInZnO-TFTs by introducing a thin ITO interlayer

We have fabricated hafnium–indium–zinc-oxide (HfInZnO) thin film transistors (TFT) with indium–tin-oxide (ITO) interlayer. Compared with conventional HfInZnO-TFT, the electrical performance and bias stability of HfInZnO-TFTs with ITO interlayer are improved. HfInZnO-TFT with 4-nm-thick ITO interlayer shows a high mobility of 7.2 cm²/V s, a low threshold voltage of 0.13 V and a better bias stability. The performance enhancement is attributed to a decrease in interface trap state and an increase in carrier concentration. It suggests that introducing ITO interlayer at the ALD Al₂O₃/HfInZnO interface is an effective way to improve the electrical performance and bias stability.     

Influence of thermal treatment on the performance of copper phthalocyanine thin-film transistors

Organic thin-film transistors (OTFTs) with bottom-gate and bottom-contact configuration based on copper phthalocyanines (CuPc) as active layer were fabricated. The performance of CuPc OTFTs was studied before and after thermal treatment on CuPc layer. The values of the threshold voltage before and after thermal treatment are −6.3 and −5.7 V, respectively. The field-effect mobility values in saturation regime of CuPc thin-film transistors before and after thermal treatment are 0.014 cm²/Vs and 0.0068 cm²/Vs, respectively. The experimental results indicate that there is a heavy decay on the mobility of CuPc based OTFTs mostly due to the crystalline morphology change induced by the thermal treatment, and absolute value of the threshold voltage after thermal treatment decreases with the decrease of the CuPc film thickness and the roughness.     

Room-temperature fabrication of ultra-thin ZrOx dielectric for high-performance InTiZnO thin-film transistors

In this letter, indium–titanium–zinc–oxide thin-film transistors with zirconium oxide (ZrO_x) gate dielectric were fabricated at room temperature. In the devices, an ultra-thin ZrO_x layer was formed as the gate dielectric by sol–gel process followed by ultraviolet (UV) irradiation. The devices can be operated under a voltage of 4 V. Enhancement mode operations with a high field-effect mobility of 48.9 cm²/V s, a threshold voltage of 1.4 V, a subthreshold swing of 0.2 V/decade, and an on/off current ratio of 10⁶ were realized. Our results demonstrate that UV-irradiated ZrO_x dielectric is a promising gate dielectric candidate for high-performance oxide devices.     

Influence of white light illumination on the performance of a-IGZO thin film transistor under positive gate-bias stress

The influence of white light illumination on the stability of an amorphous In GaZnO thin film transistor is investigated in this work. Under prolonged positive gate bias stress, the device illuminated by white light exhibits smaller positive threshold voltage shift than the device stressed under dark. There are simultaneous degradations of field-effect mobility for both stressed devices, which follows a similar trend to that of the threshold voltage shift. The reduced threshold voltage shift under illumination is explained by a competition between bias-induced interface carrier trapping effect and photon-induced carrier detrapping effect. It is further found that white light illumination could even excite and release trapped carriers originally exiting at the device interface before positive gate bias stress, so that the threshold voltage could recover to an even lower value than that in an equilibrium state. The effect of photo-excitation of oxygen vacancies within the a-IGZO film is also discussed.     

Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III–V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (t_epi) and height of source region (H_source) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (I_on) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (V_t) of 0.1 V, current gain cut-off frequency (f_T) of 12 GHz, and maximum oscillation frequency (f_max) of 283 GHz.     

Utilization of surface plasmon resonance of Au/Pt nanoparticles for highly photosensitive ZnO nanorods network based plasmon field effect transistor

Hydrothermally processed highly photosensitive ZnO nanorods based plasmon field effect transistors (PFETs) have been demonstrated utilizing the surface plasmon resonance coupling of Au and Pt nanoparticles at Au/Pt and ZnO interface. A significantly enhanced photocurrent was observed due to the plasmonic effect of the metal nanoparticles (NPs). The Pt coated PFETs showed I_on/I_off ratio more than 3 × 10⁴ under the dark condition, with field-effect mobility of 26 cm² V⁻¹ s⁻¹ and threshold voltage of −2.7 V. Moreover, under the illumination of UV light (λ = 350 nm) the PFET revealed photocurrent gain of 10⁵ under off-state (−5 V) of operation. Additionally, the electrical performance of PFETs was investigated in detail on the basis of charge transfer at metal/ZnO interface. The ZnO nanorods growth temperature was preserved at 110 °C which allowed a low temperature, economical and simple method to develop highly photosensitive ZnO nanorods network based PFETs for large scale production.     

Room-temperature and solution-processed vanadium oxide buffer layer for efficient charge injection in bottom-contact organic field-effect transistors

We introduce a room temperature and solution-processible vanadium oxide (VO_x) buffer layer beneath Au source/drain electrodes for bottom-contact (BC) organic field-effect transistors (OFETs). The OFETs with the VO_x buffer layer exhibited higher mobility and lower threshold voltages than the devices without a buffer layer. The hole mobility with VO_x was over 0.11 cm²/V with the BC geometry with a short channel length (10 μm), even without a surface treatment on SiO₂. The channel width normalized contact resistance was decreased from 98 kΩ cm to 23 kΩ cm with VO_x. The improved mobility and the reduced contact resistance were attributed to the enhanced continuity of pentacene grains, and the increased work function and adhesion of the Au electrodes using the VO_x buffer layer.     

绝缘体上硅金属氧化物半导体场效应晶体管中辐射导致的寄生效应研究

基于⁶⁰Co γ射线源研究了总剂量辐射对绝缘体上硅（silicon on insulator,SOI）金属氧化物半导体场效应晶体管器件的影响.通过对比不同尺寸器件的辐射响应,分析了导致辐照后器件性能退化的不同机制.实验表明：器件的性能退化来源于辐射增强的寄生效应;浅沟槽隔离（shallow trench isolation,STI）寄生晶体管的开启导致了关态漏电流随总剂量呈指数增加,直到达到饱和;STI氧化层的陷阱电荷共享导致了窄沟道器件的阈值电压漂移,而短沟道器件的阈值电压漂移则来自于背栅阈值耦合;在同一工艺下,尺寸较小的器件对总剂量效应更敏感.探讨了背栅和体区加负偏压对总剂量效应的影响,SOI器件背栅或体区的负偏压可以在一定程度上抑制辐射增强的寄生效应,从而改善辐照后器件的电学特性.     

用反应溅射法沉积SiO_x绝缘层的InGaZnO-TFT的光照稳定性(英文)

制备了基于反应溅射SiOx绝缘层的InGaZnO-TFT,并系统地研究了InGaZnO-TFT在白光照射下的稳定性,主要涉及到光照、负偏压、正偏压、光照负偏压和光照正偏压5种情况。结果表明,器件在光照和负偏压光照下的阈值偏移较大,而在正偏压光照情况下的阈值偏移几乎可以忽略。采用C-V方法证明阈值电压漂移是源于绝缘层/有源层附近及界面处的缺陷。另外,采用指数模式计算了缺陷态的弛豫时间。本研究的目的就是揭示InGaZnO-TFT在白光照射和偏压下的不稳定的原因。     

Statistical emission of electrons from nanocrystalline silicon quantum dot memory nodes in a few-electron MOSFET memory device

Operation of a short and narrow channel metal-oxide-semiconductor field-effect transistor (MOSFET) memory device with a few nanocrystalline Si (nc-Si) dots in the active region has been investigated at 300 and 30 K. The discrete shift of the threshold voltage (V_th) in the current-voltage characteristics that arises from the screening effect of the charge stored in the nc-Si dot above the FET channel, suggests memory operation. It is found that the value of V_th changes with temperature whereas the magnitude of the shift in V_th is independent of temperature. The lifetime of the electrons stored in the floating node has also been investigated at different read voltages.     

Extraction of density-of-states in amorphous InGaZnO thin-film transistors from temperature stress studies

The instability of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with different active layer thicknesses under temperature stress has been investigated through using the density-of-states (DOS). Interestingly, the a-IGZO TFT with 22 nm active layer thickness showed a better stability than the others, which was observed from the decrease of interfacial and semiconductor bulk trap densities. The DOS was calculated based on the experimentally-obtained activation energy (E_A), which can explain the experimental observations. We developed the high-performance Al₂O₃ TFT with 22 nm IGZO channel layer (a high mobility of 7.4 cm²/V, a small threshold voltage of 2.8 V, a high I_on/I_off 1.8 × 10⁷, and a small SS of 0.16 V/dec), which can be used as driving devices in the next-generation flat panel displays.     

沟道层厚度对室温制备的In2O3薄膜晶体管器件性能的影响

在室温下采用直流磁控溅射以SiO₂/Si为衬底制备了不同沟道层厚度的底栅式In₂O₃薄膜晶体管,讨论了沟道层厚度对底栅In₂O₃薄膜晶体管的电学性能的影响。实验结果表明:器件的特性与沟道层厚度有关,最优沟道层厚度的In₂O₃薄膜晶体管为增强型,其阈值电压为2.5 V,开关电流比约为10⁶,场效应迁移率为6.2 cm²·V^-1·s^-1。     

Enhanced electrical properties of pentacene-based organic thin-film transistors by modifying the gate insulator surface

A reliable surface treatment for the pentacene/gate dielectric interface was developed to enhance the electrical transport properties of organic thin-film transistors (OTFTs). Plasma-polymerized fluorocarbon (CFx) film was deposited onto the SiO₂ gate dielectric prior to pentacene deposition, resulting in a dramatic increase of the field-effect mobility from 0.015 cm²/(V s) to 0.22 cm²/(V s), and a threshold voltage reduction from −14.0 V to −9.9 V. The observed carrier mobility increase by a factor of 10 in the resulting OTFTs is associated with various growth behaviors of polycrystalline pentacene thin films on different substrates, where a pronounced morphological change occurs in the first few molecular layers but the similar morphologies in the upper layers. The accompanying threshold voltage variation suggests that hole accumulation in the conduction channel-induced weak charge transfer between pentacene and CFx.