总剂量效应致0.13μm部分耗尽绝缘体上硅N型金属氧化物半导体场效应晶体管热载流子增强效应

空间科学的进步对航天用电子器件提出了更高的性能需求, 绝缘体上硅(SOI)技术由此进入空间科学领域, 这使得器件的应用面临深空辐射环境与地面常规可靠性的双重挑战. 进行SOI N型金属氧化物半导体场效应晶体管电离辐射损伤对热载流子可靠性的影响研究, 有助于对SOI器件空间应用的综合可靠性进行评估. 通过预辐照和未辐照、不同沟道宽长比的器件热载流子试验结果对比, 发现总剂量损伤导致热载流子损伤增强效应, 机理分析表明该效应是STI辐射感生电场增强沟道电子空穴碰撞电离率所引起. 与未辐照器件相比, 预辐照器件在热载流子试验中的衬底电流明显增大, 器件的转移特性曲线、输出特性曲线、跨导特性曲线以及关键电学参数V_T, GM_max, ID_SAT退化较多. 本文还对宽沟道器件测试中衬底电流减小以及不连续这一特殊现象进行了讨论.     

0.18μm CMOS工艺栅极氧化膜可靠性的衬底和工艺依存性

用斜坡电压法(Voltage Ramp, V-ramp)评价了0.18μm双栅极 CMOS工艺栅极氧化膜击穿电量(Charge to Breakdown, Q_bd)和击穿电压(Voltage to Breakdown, V_bd). 研究结果表明，低压器件(1.8V)的栅极氧化膜(薄氧)p型衬底MOS电容和N型衬底电容的击穿电量值相差较小，而高压器件(3.3V)栅极氧化膜(厚氧)p衬底MOS电容和n衬底MOS电容的击穿电量值相差较大，击穿电压测试值也发现与击穿电量 关键词： 薄氧 可靠性 击穿电压 击穿电量     

单轴应变Si NMOSFET热载流子栅电流模型

热载流子效应产生的栅电流是影响器件功耗及可靠性的重要因素之一,本文基于热载流子形成的物理过程,建立了单轴应变硅NMOSFET热载流子栅电流模型,并对热载流子栅电流与应力强度、沟道掺杂浓度、栅源电压、漏源电压等的关系,以及TDDB(经时击穿)寿命与栅源电压的关系进行了分析研究.结果表明,与体硅器件相比,单轴应变硅MOS器件不仅具有较小的热载流子栅电流,而且可靠性也获得提高.同时模型仿真结果与单轴应变硅NMOSFET的实验结果符合较好,验证了该模型的可行性.     

SOI SiGe HBT电学性能研究

研究了SOI衬底上SiGe npn异质结晶体管的设计优化.给出了器件基本直流交流特性曲线,分析了与常规SiGeHBT的不同.由于SOI衬底的引入使SOI SiGe HBT成为四端器件,重点研究了衬底偏压对Gummel曲线、输出特性曲线以及雪崩电流的影响.最后仿真实现材料物理参数和几何物理参数对频率特性的改变.结果表明SOI SiGeHBT与常规器件相比具有更大的设计自由度.SOI SiGe HBT的系统分析为毫米波SOI SiGe BiCMOS电路的设计提供了有价值的参考.     

NBT导致的深亚微米PMOS器件退化与物理机理

研究了深亚微米PMOS器件在负偏压温度(negative bias temperature, NBT) 应力前后的电流电压特性随应力时间的退化，重点分析了NBT应力对PMOS器件阈值电压漂移的影响，通过实验证明了在栅氧化层和衬底界面附近的电化学反应和栅氧化层内与氢相关的元素的扩散，是PMOS器件中NBT效应产生的主要原因.指出NBT导致的PMOS器件退化依赖于反应机理和扩散机理两种机理的平衡. 关键词： 深亚微米PMOS器件 负偏压温度不稳定性 界面态 氧化层固定正电荷     

衬底位置对化学气相沉积法制备的磷掺杂p型ZnO纳米材料形貌和特性的影响

采用化学气相沉积方法,在无催化剂的条件下,通过改变衬底位置在Si(100)衬底上制备出了高取向的磷掺杂ZnO纳米线和纳米钉.测试结果表明,当衬底位于反应源上方1.5 cm处时,所制备的样品为钉状结构,而当衬底位于反应源下方1 cm处时样品为线状结构.对不同形貌磷掺杂ZnO纳米结构的生长机理进行了研究.此外,在ZnO纳米结构的低温光致发光谱中观测到了一系列与磷掺杂相关的受主发光峰.还对磷掺杂ZnO纳米结构/n-Si异质结I-V曲线进行了测试,结果表明,该器件具有良好的整流特性,纳米线和纳米钉异质结器件的开启电压分别为4.8和3.2 V.     

高k介质电导增强SOI LDMOS机理与优化设计

本文提出一种高k介质电导增强SOI LDMOS新结构（HK CE SOI LDMOS）,并研究其机理. HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻. 借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系. 结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%–18%,同时比导通电阻降低13%–20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题. 关键词： k介质')" href="#">高k介质 绝缘体上硅 (SOI) 击穿电压 比导通电阻     

高压LDMOS晶体管准饱和效应分析与建模

研究了高压LDMOS（lateral double-diffused MOS）晶体管中一种特殊的电流饱和现象——准饱和效应.借助于TCAD模拟工具,澄清了准饱和效应的物理机理是漂移区载流子的速度饱和.进而从本征漏极电压V_k入手,给出了描述LDMOS管电流饱和特性的数学模型.该模型已经通过了Matlab的编程验证,兼具准确性、计算速度和可扩展性等优点,并可进一步应用于SPICE电路模拟. 关键词： LDMOS 准饱和效应 高压     

AlGaN/GaN HEMT器件直流扫描电流崩塌机理及其物理模型

通过对AlGaN/GaN HEMT器件直流扫描情况下电流崩塌现象和机理的分析，建立了一个AlGaN/GaN HEMT器件的直流扫描电流崩塌模型.该模型从AlGaN/GaN器件工作机理出发，综合考虑了器件结构、半导体表面与界面，以及量子阱特殊结构对电流崩塌的影响.实验反复证明了该模型与实验结果有良好的一致性. 关键词： AlGaN/GaN HEMT 直流扫描 电流崩塌 模型     

发光二极管可靠性的噪声表征

通过对发光二极管内部结构的研究，发现N_t(界面态陷阱密度)和扩散电流比率 是影响发光二极管性能的重要因素，并与器件可靠性有密切关系.器件内部存在的多种噪声 中，低频1/f噪声可表征N_t和扩散电流比率.在深入研究发光二极管工作原理及1 /f噪声载流子数涨落理论和迁移率涨落理论的基础上，建立了发光二极管的电性能模型及1/ f噪声模型.在输入电流宽范围变化的条件下测量了器件的电学噪声，实验结果与理论模型符 合良好.通过对其测量结果分析，深入研究了噪声和发光二极管性能与可靠性的关系，证明 了噪声幅值越大，电流指数越接近于2，器件可靠性越差，失效率则显著增大. 关键词： 1/f噪声 发光二极管 陷阱 光功率     

Memory properties of a Ge nanocrystal MOS device fabricated by pulsed laser deposition

The charge–storage properties of Ge nanocrystal (Nc) memory devices with MOS structure have been studied. The Ge nanocrystals (Ncs) were prepared on a p-Si (100) matrix by means of pulsed laser deposition (PLD) combined with rapid annealing in the presence of Ar gas. The device is characteristic of better switching characteristics (the I _on/I _off>10⁵), low leakage current, which was attributed to the effect of Coulomb blockade preventing injection. A significant threshold-voltage shift of 0.85 V was observed when an operating voltage of 5 V was implemented on the device. The kind of hysteresis behavior in the double sweep suggests that the device has a good electrostatic control over the Ge Nc channel.     

A-188 V 7.2Ω·mm~2,P-channel high voltage device formed on an epitaxy-SIMOX substrate

This paper proposes a new n +-charge island (NCI) P-channel lateral double diffused metal-oxide semiconductor (LDMOS) based on silicon epitaxial separation by implantation oxygen (E-SIMOX) substrate.Higher concentration self-adapted holes resulting from a vertical electric field are located in the spacing of two neighbouring n +-regions on the interface of a buried oxide layer,and therefore the electric field of a dielectric buried layer (E I) is enhanced by these holes effectively,leading to an improved breakdown voltage (BV).The V B and E I of the NCI P-channel LDMOS increase to-188 V and 502.3 V/μm from 75 V and 82.2 V/μm of the conventional P-channel LDMOS with the same thicknesses SOI layer and the buried oxide layer,respectively.The influences of structure parameters on the proposed device characteristics are investigated by simulation.Moreover,compared with the conventional device,the proposed device exhibits low special on-resistance.     

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

A novel partial silicon-on-insulator (PSOI) high voltage device with a low-k (relative permittivity) dielectric buried layer (LK PSOI) and its breakdown mechanism are presented and investigated by MEDICI.At a low k value the electric field strength in the dielectric buried layer (E I) is enhanced and a Si window makes the substrate share the vertical drop,resulting in a high vertical breakdown voltage;in the lateral direction,a high electric field peak is introduced at the Si window,which modulates the electric field distribution in the SOI layer;consequently,a high breakdown voltage (BV) is obtained.The values of EI and BV of LK PSOI with kI=2 on a 2 μm thick SOI layer over 1 μm thick buried layer are enhanced by 74% and 19%,respectively,compared with those of the conventional PSOI.Furthermore,the Si window also alleviates the self-heating effect.     

Low field DC investigation of hot carrier trapping in silicon dioxide films

The experimental method used in this work is based upon the idea of nonavalanche injection of carriers heated by direct electric field. The structure consisted of an n-channel MOS transistor and two p-n junctions. The process of charge injection in this structure was investigated by studying the dependence of gate current on heating voltage. The trapping properties of the SiO₂ film were studied by monitoring the charging of the film during injection of electrons. The capture cross-sections, the trap centre concentrations and the dependence of the capture cross section on the electric field for fields between 1 MV/cm and 2.5 MV/cm were determined.     

Mismatch of dielectric constants at the interface of nanometer metal-oxide-semiconductor devices with high-<Emphasis Type="Italic">K</Emphasis> gate dielectric impacts on the inversion charge density

The comparison of the inversion electron density between a nanometer metal-oxide-semiconductor (MOS) device with high-K gate dielectric and a SiO₂ MOS device with the same equivalent oxide thickness has been discussed. A fully self-consistent solution of the coupled Schr?dinger–Poisson equations demonstrates that a larger dielectric-constant mismatch between the gate dielectric and silicon substrate can reduce electron density in the channel of a MOS device under inversion bias. Such a reduction in inversion electron density of the channel will increase with increase in gate voltage. A reduction in the charge density implies a reduction in the inversion electron density in the channel of a MOS device. It also implies that a larger dielectric constant of the gate dielectric might result in a reduction in the source–drain current and the gate leakage current.     

Electrical properties of micrometric metallic dots obtained by porous polymeric membranes

We report on the fabrication of micrometric regular metallic arrays obtained by using, as a template, a polymeric membrane with regular pores. The membranes were prepared by embedding hydrophobized silica colloids into a polymer layer and subsequently removing them. We have investigated the electronic transport properties of the metallic arrays as a function of the applied electric field and temperature. Simple current voltage (IV) characteristics present a strong switching behavior with I_ON/I_OFF ratios up to 10⁴. Different temperature dependences of the resistance in the different ranges of the applied electric field have been observed. Finally, the performances of a field effect device (FET), with the conducting channel and insulating layer consisting of a Gold dot array and a STO substrate, respectively, have been investigated. The channel resistivity has been modified at least of two orders of magnitude and a mobility of about 2 cm²/V*s has been extracted by the analysis of the FET transfer curve.     

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n⁺-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 upmum), the E_I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.     

适用于深亚微米NMOSFET ESD效应的非本地传输模型

分析了深亚微米NMOSFET在ESD应力下的非本地传输特性，分析说明了速度过冲效应可以增大漏端电流，改变器件特性. NMOSFET能量弛豫时间与器件中该点的电场、载流子速度和载流子能量密切相关，从而不能再近似为一个常数.利用蒙特卡罗仿真方法得到电子能量弛豫时间和电子高场迁移率与电子能量的关系表达式，并使用上述模型进行了ESD器件仿真，与实验结果的对比显示，使用该能量弛豫时间模型和高场迁移率模型可以得到准确的器件I-V曲线. 关键词： 静电放电 速度过冲 能量弛豫时间     

Relation between space-charge-limiting current and electric field enhancement factor at curved surface cathode

A two-dimensional solution of space-charge-limiting current for a high current vacuum diode with a spherical cathode is presented. The relation between space-charge-limiting current and electric field enhancement factor at the cathode surface for the diode with a curved surface cathode is also discussed. It is shown that compared with the current given by the conventional Child—Langmuir law, which describes the one-dimensional space-charege-limiting current, the two-dimensional space-charge-limiting current in such a diode is enhanced due to the electric-field enhancement along the cathode surface. Among practical parameter ranges, enhancement factor η_b approximately satisfies η_b ≈ Aβⁿ, where β is the electric field enhancement factor at the cathode surface, and n is a constant between 1 and 2, which is confirmed to be universal for the diodes with curved surface cathodes.     

Trapezoid mesa trench metal-oxide semiconductor barrier Schottky rectifier: an improved Schottky rectifier with better reverse characteristics

An improved structure of Schottky rectifier,called a trapezoid mesa trench metal-oxide semiconductor (MOS) barrier Schottky rectifier (TM-TMBS),is proposed and studied by two-dimensional numerical simulations.Both forward and especially better reverse I-V characteristics,including lower leakage current and higher breakdown voltage,are demonstrated by comparing our proposed TM-TMBS with a regular trench MOS barrier Schottky rectifier (TMBS) as well as a conventional planar Schottky barrier diode rectifier.Optimized device parameters corresponding to the requirement for high breakdown voltage are given.With optimized parameters,TM-TMBS attains a breakdown voltage of 186 V,which is 6.3% larger than that of the optimized TMBS,and a leakage current of 4.3×10 6 A/cm 2,which is 26% smaller than that of the optimized TMBS.The relationship between optimized breakdown voltage and some device parameters is studied.Explanations and design rules are given according to this relationship.