A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device

A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n⁺-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n⁺-regions on the interface by the force with ionized donors in the undepleted n⁺-regions, and therefore effectively enhance the electric field of the dielectric buried layer (E_I) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and E_I of the CI PSOI LDMOS increase to 631~V and 584~V/μ m from 246~V and 85.8~V/μ m for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.     

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.     

Improving breakdown voltage performance of SOI power device with folded drift region

A novel silicon-on-insulator(SOI) high breakdown voltage(BV) power device with interlaced dielectric trenches(IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer,which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges(holes) at the corner of IDT.The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.     

双面阶梯埋氧层部分SOI高压器件新结构

提出了双面阶梯埋氧层部分绝缘硅(silicon on insulator,SIO)高压器件新结构. 双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布, 耗尽层通过源极下硅窗口进一步向硅衬底扩展, 使埋氧层中纵向电场高达常规SOI结构的两倍, 且缓解了常规SOI结构的自热效应. 建立了漂移区电场的二维解析模型, 获得了器件结构参数间的优化关系. 结果表明, 在导通电阻相近的情况下, 双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58％, 温度降低10—30K. 关键词： 双面阶梯 埋氧层 调制 自热效应     

Analytical models of lateral power devices with arbitrary vertical doping profiles in the drift region

By solving the 2D Poisson's equation, analytical models are proposed to calculate the surface potential and electric field distributions of lateral power devices with arbitrary vertical doping profiles. The vertical and the lateral breakdown voltages are formulized to quantify the breakdown characteristic in completely-depleted and partially-depleted cases. A new reduced surface field (RESURF) criterion which can be used in various drift doping profiles is further derived for obtaining the optimal trade-off between the breakdown voltage and the on-resistance. Based on these models and the numerical simulation, the electric field modulation mechanism and the breakdown characteristics of lateral power devices are investigated in detail for the uniform, linear, Gaussian, and some discrete doping profiles along the vertical direction in the drift region. Then, the mentioned vertical doping profiles of these devices with the same geometric parameters are optimized, and the results show that the optimal breakdown voltages and the effective drift doping concentrations of these devices are identical, which are equal to those of the uniform-doped device, respectively. The analytical results of these proposed models are in good agreement with the numerical results and the previous experimental results, confirming the validity of the models presented here.     

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

A novel partial silicon-on-insulator (PSOI) high voltage device with a low-k (relative permittivity) dielectric buried layer (LK PSOI) and its breakdown mechanism are presented and investigated by MEDICI.At a low k value the electric field strength in the dielectric buried layer (E I) is enhanced and a Si window makes the substrate share the vertical drop,resulting in a high vertical breakdown voltage;in the lateral direction,a high electric field peak is introduced at the Si window,which modulates the electric field distribution in the SOI layer;consequently,a high breakdown voltage (BV) is obtained.The values of EI and BV of LK PSOI with kI=2 on a 2 μm thick SOI layer over 1 μm thick buried layer are enhanced by 74% and 19%,respectively,compared with those of the conventional PSOI.Furthermore,the Si window also alleviates the self-heating effect.     

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field(RESURF) silicon-on-insulator(SOI) lateral doublediffused metal–oxide–semiconductor(LDMOS) field effect transistor with n-type top(N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional(2D) Poisson's equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage(BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer(Q_(ntop)) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.     

Low Specific On-Resistance SOI LDMOS with Non-Depleted Embedded P-Island and Dual Trench Gate

A new silicon-on-insulator(SOI) trench lateral double-diffused metal oxide semiconductor(LDMOS) with a reduced specific on-resistance R_(on),sp is presented. The structure features a non-depleted embedded p-type island(EP) and dual vertical trench gate(DG)(EP-DG SOI). First, the optimized doping concentration of drift region is increased due to the assisted depletion effect of EP. Secondly, the dual conduction channel is provided by the DG when the EP-DG SOI is in the on-state. The increased optimized doping concentration of the drift region and the dual conduction channel result in a dramatic reduction in R_(on),sp. The mechanism of the EP is analyzed,and the characteristics of R_(on),sp and breakdown voltage(BV) are discussed. Compared with conventional trench gate SOI LDMOS, the EP-DG SOI decreases R_(on),sp by 47.1% and increases BV from 196 V to 212 V at the same cell pitch by simulation.     

A new analytical model of high voltage silicon on insulator （SOI） thin film devices

A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon film thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1μm which is much larger than the normal value of about 30V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (V_B,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.     

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.     

Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.     

Novel high-K with low specific on-resistance high voltage lateral double-diffused MOSFET

A novel voltage-withstand substrate with high-K (HK, k>3.9, k is the relative permittivity) dielectric and low specific on-resistance (R_on,sp) bulk-silicon, high-voltage LDMOS (HKLR LDMOS) is proposed in this paper. The high-K dielectric and highly doped interface N⁺-layer are made in bulk silicon to reduce the surface field drift region. The high-K dielectric can fully assist in depleting the drift region to increase the drift doping concentration (N_d) and reshape the electric field distribution. The highly doped N⁺-layer under the high-K dielectric acts as a low resistance path to reduce the R_on,sp. The new device with the high breakdown voltage (BV), the low R_on,sp, and the excellent figure of merit (FOM=BV²/R_on,sp) is obtained. The BV of HKLR LDMOS is 534 V, R_on,sp is 70.6 mΩ·cm², and FOM is 4.039 MW·cm^-2.     

A novel thin drift region device with field limiting rings in substrate

A novel thin drift region device with heavily doped N⁺ rings embedded in the substrate is reported, which is called the field limiting rings in substrate lateral double-diffused MOS transistor (SFLR LDMOS). In the SFLR LDMOS, the peak of the electric field at the main junction is reduced due to the transfer of the voltage from the main junction to other field limiting ring junctions, so the vertical electric field is improved significantly. A model of the breakdown voltage is developed, from which optimal spacing is obtained. The numerical results indicate that the breakdown voltage of the device proposed is increased by 76% in comparison to that of the conventional LDMOS.     

电极材料及偏压极性对氧化物介质击穿行为的影响及机制

忆阻器和能量存储电容器具有相同的三明治结构,然而两个器件需要的操作电压有明显差异,因此在同一个器件中,研究操作电压的影响因素并对操作电压进行调控,实现器件在不同领域的应用是十分必要的一个工作.本文利用反应磁控溅射技术在ITO导电玻璃、Pt/Si基底上生长了多晶ZrO_2和非晶TaO_x薄膜,选用不同金属材料Au, Ag和Al用作上电极构建了多种金属/氧化物介质/金属三明治结构的电容器,研究了器件在不同偏压极性下的击穿强度.结果发现:底电极是ITO的ZrO_2基电容器在负偏压下的击穿电场比Pt电极器件稍大.不管底电极是ITO还是Pt, Ag作为上电极时器件的击穿强度均存在明显的偏压极性依赖性,正偏压下的击穿电场减小了一个数量级;相反,在Al作为上电极的Al/TaO_x/Pt器件中,正向偏压比负向偏压下的击穿电场增加了近2倍.上述器件的不同击穿行为分别可以由氧化物电极和介质界面层间氧的迁移和重排、电化学活性金属电极的溶解迁移和还原以及化学活性金属电极与氧化物界面的氧化还原反应来解释.该实验结果对有不同操作电压要求的器件,如忆阻器和介质储能电容器等在器件设计和操作方面具有指导意义.     

Fast-switching SOI-LIGBT with compound dielectric buried layer and assistant-depletion trench

A lateral insulated gate bipolar transistor (LIGBT) based on silicon-on-insulator (SOI) structure is proposed and investigated. This device features a compound dielectric buried layer (CDBL) and an assistant-depletion trench (ADT). The CDBL is employed to introduce two high electric field peaks that optimize the electric field distributions and that, under the same breakdown voltage (BV) condition, allow the CDBL to acquire a drift region of shorter length and a smaller number of stored carriers. Reducing their numbers helps in fast-switching. Furthermore, the ADT contributes to the rapid extraction of the stored carriers from the drift region as well as the formation of an additional heat-flow channel. The simulation results show that the BV of the proposed LIGBT is increased by 113% compared with the conventional SOI LIGBT of the same length L_D. Contrastingly, the length of the drift region of the proposed device (11.2 μ) is about one third that of a traditional device (33 μ) with the same BV of 141 V. Therefore, the turn-off loss (E_OFF) of the CDBL SOI LIGBT is decreased by 88.7% compared with a conventional SOI LIGBT when the forward voltage drop (V_F) is 1.64 V. Moreover, the short-circuit failure time of the proposed device is 45% longer than that of the conventional SOI LIGBT. Therefor, the proposed CDBL SOI LIGBT exhibits a better V_F-E_OFF tradeoff and an improved short-circuit robustness.     

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance (R on,sp ) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage V d is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field E I and the breakdown voltage (BV) of ABE SOI are 545 V/μm and -587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low R on,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results.     

Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure

A vertical junction barrier Schottky diode with a high-$K$/low-$K$ compound dielectric structure is proposed and optimized to achieve a high breakdown voltage (BV). There is a discontinuity of the electric field at the interface of high-$K$ and low-$K$ layers due to the different dielectric constants of high-$K$ and low-$K$ dielectric layers. A new electric field peak is introduced in the n-type drift region of junction barrier Schottky diode (JBS), so the distribution of electric field in JBS becomes more uniform. At the same time, the effect of electric-power line concentration at the p-n junction interface is suppressed due to the effects of the high-$K$ dielectric layer and an enhancement of breakdown voltage can be achieved. Numerical simulations demonstrate that GaN JBS with a specific on-resistance ($R_{\rm on, sp}$) of 2.07 m$\Omega\cdot$cm$^{2}$ and a BV of 4171 V which is 167% higher than the breakdown voltage of the common structure, resulting in a high figure-of-merit (FOM) of 8.6 GW/cm$^{2}$, and a low turn-on voltage of 0.6 V.     

Low on-resistance high-voltage lateral double-diffused metal oxide semiconductor with a buried improved super-junction layer

A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.     

Theoretical analytic model for RESURF AlGaN/GaN HEMTs

In this paper, we propose a two-dimensional(2D) analytic model for the channel potential and electric field distribution of the RESURF AlGaN/GaN high electron mobility transistors(HEMTs). The model is constructed by two-dimensional Poisson's equation with appropriate boundary conditions. In the RESURF AlGaN/GaN HEMTs, we utilize the RESURF effect generated by doped negative charge in the AlGaN layer and introduce new electric field peaks in the device channels,thus, homogenizing the distribution of electric field in channel and improving the breakdown voltage of the device. In order to reveal the influence of doped negative charge on the electric field distribution, we demonstrate in detail the influences of the charge doping density and doping position on the potential and electric field distribution of the RESURF AlGaN/GaN HEMTs with double low density drain(LDD). The validity of the model is verified by comparing the results obtained from the analytical model with the simulation results from the ISE software. This analysis method gives a physical insight into the mechanism of the AlGaN/GaN HEMTs and provides reference to modeling other AlGaN/GaN HEMTs device.     

阶梯氧化层新型折叠硅横向双扩散功率器件

为了设计功率集成电路所需的低功耗横向功率器件, 提出了一种具有阶梯氧化层折叠硅横向双扩散金属-氧化物-半导体(step oxide folding LDMOS, SOFLDMOS)新结构. 这种结构将阶梯氧化层覆盖在具有周期分布的折叠硅表面, 利用阶梯氧化层的电场调制效应, 通过在表面电场分布中引入新的电场峰而使表面电场分布均匀, 提高了器件的耐压范围, 解决了文献提出的折叠积累型横向双扩散金属-氧化物-半导体器件击穿电压受限的问题. 通过三维仿真软件ISE分析获得, SOFLDMOS 结构打破了硅的极限关系, 充分利用了电场调制效应、多数载流子积累和硅表面导电区倍增效应, 漏极饱和电流比一般LDMOS 提高3.4倍左右, 可以在62 V左右的反向击穿电压条件下, 获得0.74 mΩ·cm²超低的比导通电阻, 远低于传统LDMOS相同击穿电压下2.0 mΩ·cm²比导通电阻, 为实现低压功率集成电路对低功耗横向功率器件的要求提供了一种可选的方案.