Capacitance characteristics of metal-oxide-semiconductor capacitors with a single layer of embedded nickel nanoparticles for the application of nonvolatile memory

This paper reports that metal-oxide-semiconductor (MOS) capacitors with a single layer of Ni nanoparticles were successfully fabricated by using electron-beam evaporation and rapid thermal annealing for application to nonvolatile memory. Experimental scanning electron microscopy images showed that Ni nanoparticles of about 5~nm in diameter were clearly embedded in the SiO₂ layer on p-type Si (100). Capacitance--voltage measurements of the MOS capacitor show large flat-band voltage shifts of 1.8~V, which indicate the presence of charge storage in the nickel nanoparticles. In addition, the charge-retention characteristics of MOS capacitors with Ni nanoparticles were investigated by using capacitance--time measurements. The results showed that there was a decay of the capacitance embedded with Ni nanoparticles for an electron charge after 10$^{4}$~s. But only a slight decay of the capacitance originating from hole charging was observed. The present results indicate that this technique is promising for the efficient formation or insertion of metal nanoparticles inside MOS structures.     

Generation of excess minority carriers in mos devices due to gamma irradiation

The effect of gamma irradiation on MOS devices prepared under different oxidation conditions Is investigated. The C-V characteristics of the devices are studied before and after exposing the latter with gamma radiations of CO⁶⁰ (1.17 and 1.33 MeV gamma rays). For MOS transistor (n-channel depletion type devices) the C-V characteristics change slightly towards the negative voltage axis and the C_min also decreases after Irradiation. For MOS capacitor (wet oxide) there is a change from high frequency C-V characteristics to low frequency C-V characteristics. In the case of a MOS capacitor (HCl grown) breakdown occurs relatively at lower voltage.     

Memory characteristics of platinum nanoparticle-embedded MOS capacitors

The capacitance characteristics of platinum nanoparticle (NP)-embedded metal–oxide–semiconductor (MOS) capacitors with gate Al₂O₃ layers are studied in this work. The capacitance versus voltage (C–V) curves obtained for a representative MOS capacitor exhibit flat-band voltage shifts, demonstrating the presence of charge storages in the platinum NPs. The counterclockwise hysteresis and flat-band voltage shift, observed from the C–V curves imply that electrons are stored in a floating gate layer consisting of the platinum NPs present between the tunneling and control oxide layers in the MOS capacitor and that these stored electrons originate from the Si substrate. Moreover, the charge remains versus time curve for the platinum NP-embedded MOS capacitor is investigated in this work.     

High temperature property studies of the 6H-SiC MOS capacitor

N-type and p-type 6H-SiC metal oxide semiconductor (MOS) capacitor samples are fabricated with a typical method,and the high frequency capacitor voltage (C-V) curves of these samples are measured at temperatures ranging from 293 to 533 K.There exists huge difference between the n-type and p-type samples.Flat-band voltage shift of the n-type sample becomes larger with temperature rising,but that of the p-type sample have very little change.This may be caused by the residual Al in the p-type oxide.Both types ...     

静电放电对GaN基功率型LED老化特性的影响

对GaN基蓝光功率型LED在老化前和老化期间施加反向人体模式静电放电(ESD),并对静电打击前后及老化前后的LED光学电学参数进行分析。实验结果及理论分析表明,ESD使LED芯片有源层及限制层中产生缺陷,最终导致电学特性及光学特性的变化。ESD给LED带来的损伤可在老化前期过程中被局部恢复,但随着老化时间推移,电参数漂移程度及光衰幅度不断增大,而老化过程中LED对ESD的敏感度增加,使LED抗ESD能力减弱。     

InGaZnO薄膜晶体管背板的栅极驱动电路静电释放失效研究

本文通过解析阵列基板栅极驱动(gate driver on array, GOA)电路中发生静电释放(electro-static discharge,ESD)的InGaZnO薄膜晶体管(InGaZnO thin-film transistor, IGZO TFT)器件发现:栅极Cu金属扩散进入了SiN_x/SiO_2栅极绝缘层;源漏极金属层成膜前就发生了ESD破坏;距离ESD破坏区域越近的IGZO TFT,电流开关比越小,直到源漏极与栅极完全短路.本文综合IGZO TFT器件工艺、GOA区与显示区金属密度比、栅极金属层与绝缘层厚度非均匀性分布等因素,采用ESD器件级分析与系统级分析相结合的方法,提出栅极Cu:SiN_x/SiO_2界面缺陷以及这三层薄膜的厚度非均匀分布是导致GOA电路中沟道宽长比大的IGZO TFT发生ESD失效的关键因素,并针对性地提出了改善方案.     

Channel length effect in a MOSFET structure by scanning capacitance microscopy

Depth dependent carrier density and trapped charges in a metal-oxide-semiconductor field effect transistor (MOSFET) like structure have been studied using scanning capacitance microscopy (SCM). For a MOSFET structure, since minority carrier can be provided by the source and drain diffusions, its response time is shorter than that of metal-oxide-semiconductor (MOS) system. So the high frequency C-V relation is slightly different from that of MOS capacitor and shows the characteristics dependent on the channel length. Bias dependent SCM images which represent the depth dependent carrier density and detrapping time constant of trapped charges in the oxide layer were observed to see the channel effect in a MOSFET structure.     

Improved dielectric and electrical properties of (Ba,Sr)TiO3 thin films using Pt/LaNiO3 as the top-electrode material

(Ba,Sr)TiO₃ (BST) capacitors grown on a LaNiO₃ (LNO) bottom electrode, with Pt (80 nm), LNO (100 nm), and double-layer Pt/LNO (80/10 nm) top electrodes have been investigated. It was found that the dielectric behavior is improved by a decrease of the electrical properties for the BST capacitor using double-layer Pt/LNO top electrodes. The dielectric constant of 100 nm-thick BST films with a Pt electrode was only 165 at 100 kHz, while that with a double-layer electrode was about 242. Correspondingly, the tunability was greatly improved from 26% to 41% with an electric field of 600 kV/cm. These have been attributed to increased interfacial capacitance density, which resulted from an improved interface, between the films and the top electrode. The dielectric loss was also reduced by using a double-layer electrode. Furthermore, the leakage current of a capacitor with a double-layer Pt/LNO electrode was one order of magnitude lower than that with a single LNO electrode. It can be explained by the fact that the weak chemical interaction between LNO (10 nm) and BST causes a high potential barrier at the interface. PACS 81.15.-z; 81.15.Cd; 77.55.+f; 77.84.Dy; 77.22.-d     

Thermal stabilities of metal bottom electrodes for Ta2O5 metal-oxide-metal capacitor structure

Thermal stabilities of various metal bottom electrodes were examined by using a Ta₂O₅ metal-oxide-metal (MOM) capacitor structure. After depositing 10-nm thick Ta₂O₅ on metal-electrode/poly-Si, we performed rapid thermal oxidation (RTO) at 850 °C for 60 s in an O₂ ambient. A chemical-vapor-deposition (CVD) WSi₂ electrode showed satisfactory thermal stability after the RTO, while other examined electrode materials exhibited thermal degradation caused by oxidation failure or interfacial reaction between the substrate poly-Si and the Ta₂O₅. After post-annealing at 650 °C for 30 min (in N₂ condition) with CVD TiN top electrode, an effective oxide thickness (T_ox) of ∼32 Å and a leakage current density of ∼10⁷ A/cm² at 1.25 V were obtained from the MOM capacitor with the WSi₂ bottom electrode. Other electrode materials, such as TiN, TiSi_x, WN_x, W, and Ta, were severely oxidized during the RTO in the MOM structures, and very poor capacitor properties were obtained in terms of T_ox and leakage current.     

High efficiency and enhanced ESD properties of UV LEDs by inserting p-GaN/p-AlGaN superlattice

Significantly improved electrostatic discharge(ESD)properties of InGaN/GaN-based UV light-emitting diode(LED)with inserting p-GaN/p-AlGaN superlattice(p-SLs)layers(instead of p-AlGaN single layer)between multiple quantum wells and Mg-doped GaN layer are reported.The pass yield of the LEDs increased from 73.53%to 93.81%under negative 2000 V ESD pulses.In addition,the light output power(LOP)and efficiency droop at high injection current were also improved.The mechanism of the enhanced ESD properties was then investigated.After excluding the effect of capacitance modulation,high-resolution X-ray diffraction(XRD)and atomic force microscope(AFM)measurements demonstrated that the dominant mechanism of the enhanced ESD properties is the material quality improved by p-SLs,which indicated less leakage paths,rather than the current spreading improved by p-SLs.     

应变Si NMOS积累区电容特性研究

积累区MOS电容线性度高且不受频率限制, 具有反型区MOS电容不可比拟的优势. 本文在研究应变Si NMOS电容C-V特性中台阶效应形成机理的基础上, 通过求解电荷分布, 建立了应变Si/SiGe NMOS积累区电容模型, 并与实验结果进行了对比, 验证了模型的正确性. 最后, 基于该模型, 研究了锗组分、应变层厚度、掺杂浓度等参数对台阶效应的影响, 为应变Si器件的制造提供了重要的指导作用. 本模型已成功用于硅基应变器件模型参数提取软件中, 为器件仿真奠定了理论基础. 关键词： 应变Si NMOS 积累区电容 台阶效应 电荷分布     

Future Direction for a Diffusion Barrier in Future High-Density Volatile and Nonvolatile Memory Devices

This article reviews the current status of high-density capacitor for volatile memory devices. The dielectric properties for both the Ta₂O₅ film and the (Ba, Sr)TiO₃ (BST) dielectric materials using either the metal organic chemical vapor deposition (MOCVD) or the atomic layer deposition (ALD) are reviewed briefly. New challenges of dielectric material for the next generation, and serious problems emerged during integration to date using Ta₂O₅ and BST. The material characteristics of many electrode materials for the high dielectric materials are introduced. We present the basic properties and integration issued for MOCVD-ruthenium (Ru). The second part of this review summarized the failure mechanisms from barrier properties of previously reported diffusion barriers and emphasizes new design concepts of diffusion barrier for high-density memory devices. Finally, the future direction for a diffusion barrier to advance high-density memory capacitors is suggested.     

晶圆键合和激光剥离工艺对GaN基垂直结构发光二极管芯片残余应力的影响

GaN基发光二极管(LED)中的残余应力状态对器件的性能和稳定性有很大影响. 通过使用三种不同的键合衬底(Al₂O₃衬底, CuW衬底和Si衬底)以及改变键合温度(290 ℃, 320 ℃, 350 ℃和380 ℃), 并且使用不同的激光能量密度(875, 945和1015 mJ·cm^-2) 进行激光剥离, 制备了不同应力状态的GaN基LED器件. 对不同条件下GaN LED进行弯曲度、Raman 散射谱测试. 实验结果表明, 垂直结构LED中的残余应力的状态是键合衬底和键合金属共同作用的结果, 而键合温度影响着垂直结构LED中的残余应力的大小. 激光剥离过程中, 一定能量密度下激光剥离工艺一般不会对芯片中的残余应力造成影响, 但是如果该工艺对GaN 层造成了微裂缝, 则会在一定程度上起到释放残余应力的作用. 使用Si衬底键合后, 外延蓝宝石衬底翘曲变大, 对应制备的GaN基垂直结构 LED中的残余应力为张应力, 并且随着键合温度的上升而变大; 而Al₂O₃和CuW衬底制备的LED中的残余应力为压应力, 但使用Al₂O₃衬底键合制备的LED中压应力随键合温度上升而一定程度变大, CuW 衬底制备的LED中压应力随键合温度上升而下降.     

Electron stimulated desorption of O+ ions: Energy dependence of the desorption efficiency from adsorbed oxygen on metal surfaces and its bearing on the mechanism

Measurements of the structure in the curve of desorption yield versus electron energy for ESD of O⁺ from β₁-oxygen on polycrystalline W and W(100), and from oxidized V are reported. They show definite structure around the core ionization thresholds of the metal atoms. This may be taken as evidence for the existence of Auger mechanisms of ESD, e.g. that proposed recently by Knotek and Feibelman for oxidic oxygen.     

Superior capacitive characteristics of RuO2 nanorods grown on carbon nanotubes

Carbon nanotubes (CNTs) were used as the electric double layer capacitor (EDLC) material and were synthesized by using thermal chemical vapor deposition (TCVD). To enhance the EDLC capacity, the ruthenium dioxide (RuO₂) nanorods were grown on CNTs by using metal organic chemical vapor deposition (MOCVD). The synthesized CNTs were the principal part and template, and the RuO₂ nanorods were grown outwardly from CNTs. The increase of effective specific area between electrode and electrolyte played an important role in enhancing the capacitance. Different concentrations of KOH were used as electrolyte to measure the capacitance to find the variation of capacitance. Moreover, the RuO₂/CNT composites demonstrated a stable cycle life. The results showed that the RuO₂/CNT composites were a promising supercapacitor device material.     

Memory characteristics and tunneling mechanism of Pt nano-crystals embedded in HfAlOx films for nonvolatile flash memory devices

A non-volatile flash memory device based on metal oxide semiconductor (MOS) capacitor structure has been fabricated using platinum nano-crystals(Pt–NCs) as storage units embedded in HfAlO_x high-k tunneling layers. Its memory characteristics and tunneling mechanism are characterized by capacitance–voltage(C–V) and flat-band voltage-time(ΔV_FB-T) measurements. A 6.5 V flat-band voltage (memory window) corresponding to the stored charge density of 2.29 × 10¹³ cm⁻² and about 88% stored electron reserved after apply ±8 V program or erase voltage for 10⁵ s at high frequency of 1 MHz was demonstrated. Investigation of leakage current–voltage(J–V) indicated that defects-enhanced Pool-Frenkel tunneling plays an important role in the tunneling mechanism for the storage charges. Hence, the Pt–NCs and HfAlO_x based MOS structure has a promising application in non-volatile flash memory devices.     

Oxidation of silicon surface with atomic oxygen radical anions

The surface oxidation of silicon （Si） wafers by atomic oxygen radical anions （O- anions） and the preparation of metal-oxide-semiconductor （MOS） capacitors on the O-oxidized Si substrates have been examined for the first time. The O- anions are generated from a recently developed O- storage-emission material of [Ca24Al2sO64]^4＋·4O^- （Cl2A7-O^- for short）. After it has been irradiated by an O- anion bean： （0.5 μA/cm^2） at 300℃ for 1-10 hours, the Si wafer achieves an oxide layer with a thickness ranging from 8 to 32 nm. X-ray photoelectron spectroscopy （XPS） results reveal that the oxide layer is of a mixture of SiO2, Si2 O3, and Si2O distributed in different oxidation depths. The features of the MOS capacitor of 〈Al electrode/SiOx/Si〉 are investigated by measuring capacitance-voltage （C - V） and current-voltage （I - V） curves. The oxide charge density is about 6.0 × 10^1 cm^-2 derived from the （C - V curves. The leakage current density is in the order of 10^-6 A/cm^2 below 4 MV/cm, obtained from the I - V curves. The O- anions formed by present method would have potential applications to the oxidation and the surface-modification of materials together with the preparation of semiconductor devices.     

Formation dynamics of bipolaron in a metal/polymer/metal structure

Charge injection process from metal electrode to a nondegenerate polymer in a metal/ polymer/ metal structure has been investigated by using a nonadiabatic dynamic method. We demonstrate that the dynamical formation of a bipolaron sensitively depends on the strength of applied electric field, the work function of metal electrode, and the contact between the polymer and the electrode. For a given bias applied to one of the electrode (V₀) and coupling between the electrode and the polymer (t^′), such as V₀=0.79 eV and t^′=1 eV, the charge injection process depending on the electric field can be divided into the following three cases: (1) in the absence of the electric field, only one electron tunnels into the polymer to form a polaron near the middle of the polymer chain; (2) at low electric fields, two electrons transfer into the polymer chain to form a bipolaron; (3) at higher electric fields, bipolaron can not be formed in the polymer chain, electrons are transferred from the left electrode to right electrode through the polymer one by one accompanying with small irregular lattice deformations.     

Metal-electrode-free inverted organic photovoltaics using electrospray-deposited PEDOT:PSS and spin-coated HAT-CN exciton blocking layer

Poly(3,4-ethylenedioxythiophene)-poly(styrene sulfonate) (PEDOT:PSS) films were fabricated using an electrospray deposition (ESD) method. The ESD PEDOT:PSS films exhibited higher PSS content on the surface than spin-coated PEDOT:PSS films, which results in a higher work function. Based on this result, metal-electrode-free inverted organic photovoltaics (OPVs) were fabricated. The ESD PEDOT:PSS was used as the top electrode on the poly(3-hexythiophene-2,5-diyl) (P3HT):[6,6]-phenyl C₆₁ butyric acid methyl ester (PCBM) light-absorbing layer. The power conversion efficiency (PCE) of OPVs was significantly increased with the 1,4,5,8,9,11-hexaazatriphenylene hexacarbonitrile layer. The improved PCE would be attributed to the suppression of exciton quenching at the P3HT:PCBM and PEDOT:PSS interface.     

Non-ideal effects of MOS capacitor in a switched capacitor waveform recorder ASIC

SCAs(Switched Capacitor Arrays) have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents( 4m A max) and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 m W/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 m V with 625 k Hz full-scale sine wave as input, sampling at 40 MSPS(Mega-samples per Second) and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 m V. The test results validate the feasibility of the MOS capacitor.