Novel approaches for low cost fabrication of SOI

Two trials for low cost manufacture of silicon-on-insulator (SOI) wafers were implemented. Low dose separation by implantation of oxygen (SIMOX) procedure has been conducted on a beam-line ion implanter with mass analyzer. The energy dependence of the formed SOI structure was studied at varied implant dosages. The integrity of the buried oxide (BOX) layer was examined by transmission electron microscopy (TEM) and the threading dislocation in the top silicon layer was evaluated by Secco technique. The results indicated that not only the implanted oxygen dose but also the oxygen ion energy plays an important role in the formation of SOI structure with good crystallinity of top silicon, sharp Si/SiO₂ interfaces and highly integrated BOX layer free of silicon inclusion. For separation by plasma implantation of oxygen (SPIMOX) approach, water plasma, rather than oxygen plasma, was employed to avoid oxygen spread in the implant depth profile. The SPIMOX process using water plasma was carried out on a beam-line ion implanter without mass selector to simulate the plasma implantation procedure. Cross-sectional TEM study revealed that uniform BOX layer was formed under single crystal silicon superficial layer with the present approach. The interfaces between silicon superficial layer, BOX layer and bulk silicon were smooth and sharp. An implant dose window has been identified for fabricating the desirable SOI structure.     

Dual material insulator SOI-LDMOSFET: A novel device for self-heating effect improvement

The silicon-on-insulator (SOI) power devices show good electrical performance but they suffer from inherent self-heating effect (SHE), which limits their operation at high current levels. The SHE effect is because of low thermal conductivity of the buried oxide layer. In this paper we propose a novel silicon on insulator lateral double diffused MOSFET (SOI-LDMOSFET) where the buried insulator layer under the active region consists of two materials in order to decrease the SHE. The proposed structure is called dual material buried insulator SOI-LDMOSFET (DM-SOI). Using two-dimensional and two-carrier device simulation, we demonstrate that the heat dissipation and the SHE can be improved in a conventional SOI-LDMOSFET by replacement of the buried oxide with dual material buried insulator (silicon nitride and silicon oxide) beneath the active region. The heat generated in the active silicon layer can be flowed through the buried silicon nitride layer to the silicon substrate easily due to high thermal conductivity of silicon nitride. Furthermore, the channel temperature is reduced, negative drain current slope is mitigated and electron and hole mobility is increased during high-temperature operation. The simulated results show that silicon nitride is a suitable alternative to silicon dioxide as a buried insulator in SOI structures, and has better performance in high temperature.     

A new analytical model of high voltage silicon on insulator （SOI） thin film devices

A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon film thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1μm which is much larger than the normal value of about 30V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (V_B,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.     

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.     

SOIM新结构的制备及其性能的研究

制备在以SiO2为绝缘埋层的SOI材料上的电子器件存在着自加热问题.为减少自加热效应和满足一些特殊器件/电路的要求，利用多孔硅外延转移技术制备出以二氧化硅和氮化硅为多绝缘埋层的SOI新结构.高分辨率透射电镜和扩展电阻测试结果表明得到的SOIM新结构具有很好的结构和电学性能，退火后的氮化硅埋层为非晶结构.     

Fabrication of freestanding nanoscale gratings on silicon-on-insulator wafer

We report a bottom-up process for the fabrication of freestanding nanoscale gratings on silicon-on-insulator (SOI) wafer. Freestanding membrane devices suffer deflection due to the residual stress of the buried oxide layer of SOI wafer. The deflection will affect the device shape and result in the fracture problem for devices fabricated on thin silicon membrane. The bottom-up process is developed to overcome the fabrication issue for thin silicon membrane gratings. The silicon handle layer is removed through back wafer etching of silicon, where the buried oxide layer acts as an etch stop layer. The grating structures are then defined on thin silicon device layer by electron beam lithography and generated by fast atom beam etching. The grating structures are finally released in vapor HF to form the freestanding nanoscale gratings. The freestanding linear/circular gratings, 1,500-nm period grating with the grating width of 200- and 850-nm period grating with the grating width of 100 nm, are successfully achieved on 260-nm silicon device layer.     

基于第一性原理计算的掺杂柔性黑硅吸收光谱特性分析

针对宽波段微型光谱仪缺乏宽波段柔性探测器这一难题,提出了一种在紫外-可见-近红外波段内具有高吸收效率的掺杂柔性黑硅作为探测器吸光材料。首先,基于第一性原理计算了S和F元素掺杂后柔性黑硅的电子结构、能带结构和紫外-可见-近红外波段的光学吸收特性,得到了不同元素及浓度掺杂时,柔性黑硅的光学吸收系数。其次,将第一性原理计算结果与时域有限差分算法相结合,建立了柔性黑硅的吸收光谱模型。结果表明,掺入S和F元素后柔性黑硅的能带带隙均减小,吸收截止波长发生红移,且掺杂浓度越高,光学吸收系数越大。在1 500 nm波长处,50%浓度的S元素掺杂黑硅的吸光系数是1.5%浓度的S元素掺杂黑硅的吸光系数的8.3倍,50%浓度的F元素掺杂黑硅的吸光系数是1.5%浓度的F元素掺杂黑硅的吸光系数的3倍。在相同掺杂条件下,表面具有小尺寸微结构的柔性黑硅在近红外波段具有最高的吸收效率。最后,测试了制作的柔性黑硅样品,其吸光效率在紫外-可见波段高于95%,在近红外波段为70%~80%。     

硅键合SOI平面光波导探索

本文分析了ＳＩＭＯＸ／ＳＯＩ和ＤＷＢ／ＳＯＩ结构的性能特点。尝试用ＤＷＢ／ＳＯＩ材料制备不同波导层厚度的平面光波导样品，并测试了１．１５μｍ和１．５２３μｍ激光的ＴＥ和ＴＭ模的传输损耗。１．５２３μｍ光的ＴＥ模的最小传输损耗已达０．２７ｄＢ／ｃｍ。说明ＤＷＢ／ＳＯＩ材料是一种有潜力的光波导材料。     

离子注入形成SOI结构的界面及埋层的俄歇能谱研究

本文中研究了O⁺(200keV,1.8×10¹⁸/cm²)和N⁺(190keV,1.8×10¹⁸/cm²)注入Si形成SOI(Silicon on Insulator)结构的界面及埋层的化学组成。俄歇能谱的测量和研究结果表明:注O⁺的SOI结构在经1300℃,5h退火后,其表层Si和氧化硅埋层的界面存在一个不饱和氧化硅状态,氧化硅埋层是由SiO₂相和这不饱和氧化硅态组成,而且氧化硅埋层和体硅界面不同于表层Si和氧化硅埋层界面;注N⁺的SOI结构在经1200℃,2h退火后,其氮化硅埋层中存在一个富N的疏松夹层,表层Si和氮化硅埋层界面与氮化硅埋层和体硅界面性质亦不同。这些结果与红外吸收和透射电子显微镜及离子背散射谱的分析结果相一致。还对两种SOI结构界面与埋层的不同特征的原因进行了分析讨论。 关键词：     

Stress evolution influenced by oxide charges on GaN metal–organic chemical vapor deposition on silicon-on-insulator substrate

GaN epilayers have been deposited on silicon-on-insulator (SOI) and bulk silicon substrates. The stress transition thickness and the initial compressive stress of a GaN epilayer on the SOI substrate are larger than those on the bulk silicon substrate, as shown in in situ stress measurement results. It is mainly due to the difference of the three-dimensional island density and the threading dislocation density in the GaN layer. It can increase the compressive stress in the initial stage of growth of the GaN layer, and helps to offset the tensile stress generated by the lattice mismatch. PACS 81.15.Gh     

具有L型源极场板的双槽绝缘体上硅高压器件新结构

为了提高小尺寸绝缘体上硅(SOI)器件的击穿电压,同时降低器件比导通电阻,提出了一种具有L型源极场板的双槽SOI高压器件新结构.该结构具有如下特征:首先,采用了槽栅结构,使电流纵向传导面积加宽,降低了器件的比导通电阻;其次,在漂移区引入了Si O2槽型介质层,该介质层的高电场使器件的击穿电压显著提高;第三,在槽型介质层中引入了L型源极场板,该场板调制了漂移区电场,使优化漂移区掺杂浓度大幅增加,降低了器件的比导通电阻.二维数值仿真结果表明:与传统SOI结构相比,在相同器件尺寸时,新结构的击穿电压提高了151%,比导通电阻降低了20%;在相同击穿电压时,比导通电阻降低了80%.与相同器件尺寸的双槽SOI结构相比,新结构保持了双槽SOI结构的高击穿电压特性,同时,比导通电阻降低了26%.     

Improvement of total-dose irradiation hardness of silicon-on-insulator materials by modifying the buried oxide layer with ion implantation

The hardening of the buried oxide (BOX) layer of separation by implanted oxygen (SIMOX) silicon-on-insulator (SOI) wafers against total-dose irradiation was investigated by implanting ions into the BOX layers. The tolerance to total-dose irradiation of the BOX layers was characterized by the comparison of the transfer characteristics of SOI NMOS transistors before and after irradiation to a total dose of 2.7 Mrad(SiO₂. The experimental results show that the implantation of silicon ions into the BOX layer can improve the tolerance of the BOX layers to total-dose irradiation. The investigation of the mechanism of the improvement suggests that the deep electron traps introduced by silicon implantation play an important role in the remarkable improvement in radiation hardness of SIMOX SOI wafers.     

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n⁺-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 upmum), the E_I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.     

微纳混合结构黑硅的制备及其关键工艺技术讨论

黑硅是一种能大幅提高器件光电转换效率的新型电子材料,微纳混合结构黑硅是一种比普通黑硅材料更高效的新型黑硅材料,如何制备出大面积、形貌特征好、表面洁净度高的黑硅材料是制备高效的黑硅太阳能电池的前提。首先,利用湿法腐蚀方法,通过设计合适的反应固体装置和良好的工艺控制手段,在金字塔硅表面制备了大面积的微纳混合结构黑硅;然后,对其制备的关键工艺技术进行了研究讨论。实验结果表明,该方法制备的微纳混合结构黑硅具有形貌特征好、表面洁净度高和低表面反射率等特征。有效去除表面银沉积物后,该黑硅在300~1 100 nm范围内的加权平均反射率低至4.06%。该制备工艺方法适用于大面积高效微纳混合结构黑硅的规模制备,在高效黑硅太阳能电池领域具有重要的应用价值。     

Energy transfer at optical frequencies to silicon-on-insulator structures

The refractive-index distribution that is intrinsic to the silicon-on-insulator (SOI) material system makes it possible for optical-frequency guided waves to be confined by the SOI silicon layer. The same refractive-index distribution is unusual among nonmetals in that it is possible for those SOI guided waves to interact strongly with nearby optical-frequency radiators, absorbers, and scatterers (e.g., atoms, molecules, and nanoparticles). We calculate the guided-mode excitation efficiency for an exterior particle near the SOI surface and show that it can attain values greater than 80% under appropriate conditions, thus showing that the SOI waveguide system is an attractive platform for the study of optical-frequency surface interactions.     

Some material structural properties of SOI substrates produced by SDB technology

SOI substrates have been produced by silicon direct bonding (SDB) technology. Thermal oxides ranging in thickness from native oxide to 1 μm or even more, on either or both wafers have been bonded successfully. The fracture strength of the SOI layer is 130–200 kg/cm² which is similar to the value of intrinsic bulk silicon. Dislocations have been shown to be concentrated on the backsides of the substrate and no additional defects have been developed within 80 μm of the Si-SiO₂ bonding area. Mobility and minority carrier lifetime similar to that of the original bulk silicon have been obtained after annealing.     

基于智能剥离技术的SOI材料制备

优化了硅片低温直接键合与智能剥离技术的工艺流程，在550℃，2.1×10^-2 Pa条件下制备了SOI材料，其顶层单晶Si膜的表面粗糙度为8.5 nm，缺陷密度为90 cm^-2，键合强度达到153.7 kg/cm²，形成的SOI结构除了可以形成三维集成电路中有源层间良好的绝缘层，避免了高温过程对有源层器件结构、材料及性能的影响，还能为三维集成电路后续有源层的制造提供高质量的单晶硅材料. 关键词： 绝缘体上硅 智能剥离 低温直接键合     

氮氟复合注入对注氧隔离SOI材料埋氧层内固定正电荷密度的影响

为了抑制埋层注氮导致的埋层内正电荷密度的上升, 本文采用氮氟复合注入方式, 向先行注氮的埋层进行了注氮之后的氟离子注入, 并经适当的退火, 对埋层进行改性. 利用高频电容-电压 (C-V) 表征技术, 对复合注入后的埋层进行了正电荷密度的表征. 结果表明, 在大多数情况下, 氮氟复合注入能够有效地降低注氮埋层内的正电荷密度, 且其降低的程度与注氮后的退火时间密切相关. 分析认为, 注氟导致注氮埋层内的正电荷密度降低的原因是在埋层中引入了与氟相关的电子陷阱. 另外, 实验还观察到, 在个别情况下, 氮氟复合注入引起了埋层内正电荷密度的进一步上升. 结合测量结果, 讨论分析了该现象产生的原因. 关键词： 绝缘体上硅(SOI) 材料 注氮 注氟 埋氧层正电荷密度     

双面阶梯埋氧层部分SOI高压器件新结构

提出了双面阶梯埋氧层部分绝缘硅(silicon on insulator,SIO)高压器件新结构. 双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布, 耗尽层通过源极下硅窗口进一步向硅衬底扩展, 使埋氧层中纵向电场高达常规SOI结构的两倍, 且缓解了常规SOI结构的自热效应. 建立了漂移区电场的二维解析模型, 获得了器件结构参数间的优化关系. 结果表明, 在导通电阻相近的情况下, 双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58％, 温度降低10—30K. 关键词： 双面阶梯 埋氧层 调制 自热效应     

High-index contrast grating based broadband out-coupler on SOI

An efficient broadband out-coupler on silicon-on-insulator (SOI) with high-index contrast grating (HCG) is proposed. The presence of a silicon-air (high-index contrast) grating on the top silicon layer in SOI allows a strong interaction between the guided mode and the grating. The broadband design of the out-coupler is presented by optimising the various grating parameters. The design analysis and simulation of such an out-coupler is performed with finite difference method. Coupling efficiency of 54% is achieved over an ultra-wide wavelength range from 1500 nm to 1650 nm.