Three-dimensional vertical ZnO transistors with suspended top electrodes fabricated by focused ion beam technology

Three-dimensional(3D)vertical architecture transistors represent an important technological pursuit,which have distinct advantages in device integration density,operation speed,and power consumption.However,the fabrication processes of such 3D devices are complex,especially in the interconnection of electrodes.In this paper,we present a novel method which combines suspended electrodes and focused ion beam(FIB)technology to greatly simplify the electrodes interconnection in 3D devices.Based on this method,we fabricate 3D vertical core-double shell structure transistors with ZnO channel and Al₂O₃ gate-oxide both grown by atomic layer deposition.Suspended top electrodes of vertical architecture could be directly connected to planar electrodes by FIB deposited Pt nanowires,which avoid cumbersome steps in the traditional 3D structure fabrication technology.Both single pillar and arrays devices show well behaved transfer characteristics with an Ion/Ioff current ratio greater than 106 and a low threshold voltage around 0 V.The ON-current of the 2×2 pillars vertical channel transistor was 1.2μA at the gate voltage of 3 V and drain voltage of 2 V,which can be also improved by increasing the number of pillars.Our method for fabricating vertical architecture transistors can be promising for device applications with high integration density and low power consumption.     

Technology demonstration of a novel poly-Si nanowire thin film transistor

A simple process flow method for the fabrication of poly-Si nanowire thin film transistors(NW-TFTs) without advanced lithographic tools is introduced in this paper.The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a spacer formation technique.The electrical and temperature characteristics of the developed NW-TFTs are measured in detail and compared with those of conventional planar TFTs(used as a control).The as-demonstrated NW-TFT exhibits a small subthreshold swing(191 mV/dec),a high ON/OFF ratio(8.5 × 10~7),alow threshold voltage(1.12 V),a decreased OFF-state current,and a low drain-induced-barrier lowering value(70.11 mV/V).The effective trap densities both at the interface and grain boundaries are also significantly reduced in the NW-TFT.The results show that all improvements of the NW-TFT originate from the enhanced gate controllability of the multi-gate over the channel.     

Nanoscale control of low-dimensional spin structures in manganites

Due to the upcoming demands of next-generation electronic/magnetoelectronic devices with low-energy consumption,emerging correlated materials(such as superconductors,topological insulators and manganites) are one of the highly promising candidates for the applications.For the past decades,manganites have attracted great interest due to the colossal magnetoresistance effect,charge-spin-orbital ordering,and electronic phase separation.However,the incapable of deterministic control of those emerging low-dimensional spin structures at ambient condition restrict their possible applications.Therefore,the understanding and control of the dynamic behaviors of spin order parameters at nanoscale in manganites under external stimuli with low energy consumption,especially at room temperature is highly desired.In this review,we collected recent major progresses of nanoscale control of spin structures in manganites at low dimension,especially focusing on the control of their phase boundaries,domain walls as well as the topological spin structures(e.g.,skyrmions).In addition,capacitor-based prototype spintronic devices are proposed by taking advantage of the above control methods in manganites.This capacitor-based structure may provide a new platform for the design of future spintronic devices with low-energy consumption.     

Heteromaterial-gate line tunnel field-effect transistor based on Si/Ge heterojunction

A Si/Ge heterojunction line tunnel field-effect transistor(LTFET) with a symmetric heteromaterial gate is proposed.Compared to single-material-gate LTFETs, the heteromaterial gate LTFET shows an off-state leakage current that is three orders of magnitude lower, and steeper subthreshold characteristics, without degradation in the on-state current. We reveal that these improvements are due to the induced local potential barrier, which arises from the energy-band profile modulation effect. Based on this novel structure, the impacts of the physical parameters of the gap region between the pocket and the drain, including the work-function mismatch between the pocket gate and the gap gate, the type of dopant, and the doping concentration, on the device performance are investigated. Simulation and theoretical calculation results indicate that the gap gate material and n-type doping level in the gap region should be optimized simultaneously to make this region fully depleted for further suppression of the off-state leakage current.