沟道层厚度对室温制备的In2O3薄膜晶体管器件性能的影响

在室温下采用直流磁控溅射以SiO₂/Si为衬底制备了不同沟道层厚度的底栅式In₂O₃薄膜晶体管,讨论了沟道层厚度对底栅In₂O₃薄膜晶体管的电学性能的影响。实验结果表明:器件的特性与沟道层厚度有关,最优沟道层厚度的In₂O₃薄膜晶体管为增强型,其阈值电压为2.5 V,开关电流比约为10⁶,场效应迁移率为6.2 cm²·V^-1·s^-1。     

A broadband self-powered UV photodetector of aβ-Ga2O3/γ-CuI p–n junction

The symmetric Ti/Au bi-layer point electrodes have been successfully patterned on theβ-Ga;O;films which are prepared by metal–organic chemical vapor deposition(MOCVD)and theγ-Cu I films which are prepared by spin-coating.The fabricated heterojunction has a large open circuit voltage(Voc)of 0.69 V,desired for achieving self-powered operation of a photodetector.Irradiated by 254-nm ultraviolet(UV)light,when the bias voltage is-5 V,the dark current(Idark)of the device is 0.47 p A,the photocurrent(Iphoto)is-50.93 n A,and the photo-to-dark current ratio(Iphoto/Idark)reaches about 1.08×10;.The device has a stable and fast response speed in different wavelengths,the rise time(τr)and decay time(τd)are 0.762 s and 1.741 s under 254-nm UV light illumination,respectively.While theτr andτd are 10.709 s and7.241 s under 365-nm UV light illumination,respectively.The time-dependent(I–t)response(photocurrent in the order of10-10 A)can be clearly distinguished at a small light intensity of 1μW·cm;.The internal physical mechanism affecting the device performances is discussed by the band diagram and charge carrier transfer theory.     

基于P掺杂SiO2为栅介质的超低压侧栅薄膜晶体管

在室温下利用等离子体增强化学气相沉积法(PECVD)制备的颗粒膜P掺杂SiO₂为栅介质, 使用磁控溅射方法利用一步掩模法制备出一种新型结构的侧栅薄膜晶体管. 由于侧栅薄膜晶体管具有独特的结构, 在射频磁控溅射过程中, 仅仅利用一块镍掩模板, 无需复杂的光刻步骤, 就可同时沉积出氧化铟锡(ITO)源、漏、栅电极和沟道, 因此, 这种方法极大地简化了制备流程, 降低了工艺成本. 实验结果表明, 在P掺杂SiO₂栅介质层与沟道层界面处形成了超大的双电层电容(8 μF/cm²), 这使得这类晶体管具有超低的工作电压1 V, 小的亚阈值摆幅82 mV/dec、高的迁移率18.35 cm²/V·s和大的开关电流比1.1×10⁶. 因此, 这种P掺杂SiO₂双电层超低压薄膜晶体管将有望应用于低能耗便携式电子产品以及新型传感器领域. 关键词： 2')" href="#">P掺杂SiO₂ 侧栅薄膜晶体管 双电层(EDL) 超低压     

MoS2/Si tunnel diodes based on comprehensive transfer technique

Due to the pristine interface of the 2D/3D face-tunneling heterostructure with an ultra-sharp doping profile, the 2D/3D tunneling field-effect transistor (TFET) is considered as one of the most promising low-power devices that can simultaneously obtain low off-state current (I_OFF), high on-state current (I_ON) and steep subthreshold swing (SS). As a key element for the 2D/3D TFET, the intensive exploration of the tunnel diode based on the 2D/3D heterostructure is in urgent need. The transfer technique composed of the exfoliation and the release process is currently the most common approach to fabricating the 2D/3D heterostructures. However, the well-established transfer technique of the 2D materials is still unavailable. Only a small part of the irregular films can usually be obtained by mechanical exfoliation, while the choice of the chemical exfoliation may lead to the contamination of the 2D material films by the ions in the chemical etchants. Moreover, the deformation of the 2D material in the transfer process due to its soft nature also leads to the nonuniformity of the transferred film, which is one of the main reasons for the presence of the wrinkles and the stacks in the transferred film. Thus, the large-scale fabrication of the high-quality 2D/3D tunnel diodes is limited. In this article, a comprehensive transfer technique that can mend up the shortages mentioned above with the aid of the water and the thermal release tape (TRT) is proposed. Based on the method we proposed, the MoS₂/Si tunnel diode is experimentally demonstrated and the transferred monolayer MoS₂ film with the relatively high crystal quality is confirmed by atomic force microscopy (AFM), scanning electron microscopy (SEM), and Raman characterizations. Besides, the prominent negative differential resistance (NDR) effect is observed at room temperature, which verifies the relatively high quality of the MoS₂/Si heterojunction. The bilayer MoS₂/Si tunnel diode is also experimentally fabricated by repeating the transfer process we proposed, followed by the specific analysis of the electrical characteristics. This study shows the advantages of the transfer technique we proposed and indicates the great application foreground of the fabricated 2D/3D heterostructure for ultralow-power tunneling devices.     

Al_2O_3薄层修饰SiN_x绝缘层的IGZO-TFTs器件的性能研究

采用原子层沉积工艺(ALD)生长均匀致密的三氧化二铝(Al2O3)薄层对氮化硅(Si Nx)绝缘层进行修饰,研究了铟镓锌氧薄膜晶体管(IGZO-TFTs)器件的性能。当Al2O3修饰层厚度为4 nm时,绝缘层-有源层界面的最大缺陷态密度相比于未修饰器件降低了17.2%,器件性能得到显著改善。场效应迁移率由1.19 cm2/(V·s)提高到7.11 cm2/(V·s),阈值电压由39.70 V降低到25.37 V,1 h正向偏压应力下的阈值电压漂移量由2.19 V减小到1.41 V。     

Influence of the transparency of tunnel barriers in Nb/Al2O3/Al/Al2O3/Nb junctions on transport properties

The transparency of the tunnel barriers in double-barrier junctions influences the critical current density and the form of the current–voltage characteristics (IVC). Moreover, the barrier asymmetry is an important parameter, which has to be controlled in the technological process. We have performed a systematic study of the influence of the barrier transparency on critical current, I_C, and normal resistance, R_N, by preparing SIS and SINIS junctions under identical technological conditions and comparing their transport properties. We have fabricated Nb/Al₂O₃/Nb and Nb/Al₂O₃/Al/Al₂O₃/Nb devices with different current densities using a conventional fabrication process, varying pressure and oxidation time. The thickness of the Al middle electrode in all Nb/Al₂O₃/Al/Al₂O₃/Nb junctions was 6 nm. Patterning of the multilayers was done using conventional photolithography and the selective niobium etching process. The current density of SIS junctions was changed in the range from 0.5 to 10 kA/cm². At the same conditions the current density of SINIS devices revealed 1–100 A/cm² with non-hysteretic IVC and characteristic voltages, I_CR_N, of up to 200 μV. By comparing the experimental and theoretical temperature dependence of the I_CR_N product we estimated the barrier transparency and its asymmetry. The comparison shows a good agreement of experimental data with the theoretical model of tunneling through double-barrier structures in the dirty limit and provides the effective barrier transparency parameter γ_eff≈300. A theoretical framework is developed to study the influence of the barrier asymmetry on the current–phase relationship and it is proposed to determine the asymmetry parameter by measuring the critical current suppression as function of applied microwave power. The theoretical approach to determine the non-stationary properties of double-barrier junctions in the adiabatic regime is formulated and the results of calculations of the I–V characteristics are given in relevant limits. The existence and the magnitude of a current deficit are predicted as function of the barrier asymmetry.     

Current oscillation in GaN-HEMTs with p-GaN islands buried layer for terahertz applications

A GaN-based high electron mobility transistor (HEMT) with p-GaN islands buried layer (PIBL) for terahertz applications is proposed. The introduction of a p-GaN island redistributes the electric field in the gate-drain channel region, thereby promoting the formation of electronic domains in the two-dimensional electron gas (2DEG) channel. The formation and regulation mechanism of the electronic domains in the device are investigated using Silvaco-TCAD software. Simulation results show that the 0.2 μ m gate HEMT with a PIBL structure having a p-GaN island doping concentration (N_p) of 2.5×10¹⁸ cm^-3-3×10¹⁸ cm^-3 can generate stable oscillations up to 344 GHz-400 GHz under the gate-source voltage (V_gs) of 0.6 V. As the distance (D_p) between the p-GaN island and the heterojunction interface increases from 5 nm to 15 nm, the fundamental frequency decreases from 377 GHz to 344 GHz, as well as the ratio of oscillation current amplitude of the fundamental component to the average component I_f1/I_avg ranging from 2.4% to 3.84%.     

Development of highly integrated RSFQ circuits on the basis of intrinsically shunted Josephson junctions

At PTB, for application in rapid single flux quantum (RSFQ) and voltage standard circuits, the development of highly integrated SDE circuits is focused on devices based on intrinsically shunted Josephson junctions in the SINIS and SNS technologies. In SINIS technology, the fabrication process has been optimized to values of the critical current density of j_C=500 A/cm² and the characteristic voltage of V_C=190 μV. To raise the circuit integration level, successive steps of development are shown by the example of the layout of an elementary RSFQ cell designed for higher values of j_C. In SNS technology, a fabrication process has been developed to produce small ramp-type junctions with contact areas smaller than 0.4 μm² and with values for j_C and V_C of about j_C=200 kA/cm² and V_C=20 μV. The design allows the SNS junction size to be further reduced down to the deep sub-micron range.     

Ferroelectric effect and equivalent polarization charge model of PbZr_(0.2)Ti_(0.8)O_3 on AlGaN/GaN MIS-HEMT

PbZr_(0.2)Ti_(0.8)O_3(PZT) gate insulator with the thickness of 30 nm is grown by pulsed laser deposition(PLD) in AlGa N/Ga N metal–insulator–semiconductor high electron mobility transistors(MIS-HEMTs). The ferroelectric effect of PZT Al Ga N/Ga N MIS-HEMT is demonstrated. The polarization charge in PZT varies with different gate voltages. The equivalent polarization charge model(EPCM) is proposed for calculating the polarization charge and the concentration of two-dimensional electron gas(2 DEG). The threshold voltage(Vth) and output current density(IDS) can also be obtained by the EPCM. The theoretical values are in good agreement with the experimental results and the model can provide a guide for the design of the PZT MIS-HEMT. The polarization charges of PZT can be modulated by different gate-voltage stresses and the Vthhas a regulation range of 4.0 V. The polarization charge changes after the stress of gate voltage for several seconds. When the gate voltage is stable or changes at high frequency, the output characteristics and the current collapse of the device remain stable.     

SiO2固态电解质中的质子特性对氧化物双电层薄膜晶体管性能的影响

本文采用等离子体增强化学气相沉积技术(PECVD)在室温条件下制备了具有双电层效应的二氧化硅(SiO₂) 固体电解质薄膜, 并以此SiO₂薄膜作为栅介质制备了氧化铟锌(IZO)双电层薄膜晶体管. 本文系统地研究了SiO₂固体电解质中的质子特性对双电层薄膜晶体管性能的影响, 研究结果表明, 经过纯水浸泡的SiO₂固体电解质薄膜可以诱导出较多的可迁移质子, 因此表现出较大的双电层电容. 由于SiO₂固体电解质薄膜具有质子迁移特性, 晶体管的转移特性曲线呈现出逆时针方向的洄滞现象, 并且这一洄滞效应随着栅极电压扫描速率的增加而增大. 进一步对薄膜晶体管的偏压稳定性进行测试, 发现晶体管的阈值电压的变化遵循了拉升指数函数(stretched exponential function)关系.     

Si(100)衬底上n-3C-SiC/p-Si异质结构研究

利用LPCVD方法在Si(100)衬底上获得了3C-SiC外延膜,扫描电子显微镜(SEM)研究表明3C-SiC/p-Si界面平整、光滑,无明显的坑洞形成。研究了以In和Al为接触电极的3C-SiC/p-Si异质结的I-V,C-V特性及I-V特性的温度依赖关系,比较了In电极的3C-SiC/p-Si异质结构和以SiGe作为缓冲层的3C-SiC/SiGe/p-Si异质结构的I-V特性,实验发现引入SiGe缓冲层后,器件的反向击穿电压由40V提高到70V以上。室温下Al电极3C-SiC/p-Si二极管的最大反向击穿电压接近100V,品质因子为1.95。     

Fabrication and characteristics of all YBCO sandwich-type junctions using highly crystalline DC sputtered superconducting a-axis oriented Y1Ba2Cu3O7-x films

We report on the fabrication and characteristics of sandwich-type tunnel junctions with highly crystalline sputtered a-axis oriented thin film of Y₁Ba₂Cu₃O_7-x (YBC) as the base and the counter electrode. The junctions have been fabricated on SrTiO₃ (100) and MgO (100) substrates. A non-superconducting phase of YBC corresponding to a lattice constant of 4.08 Å is used as the barrier layer making this an all YBC sandwich junction. For all temperatures below T_ce (R=0) of the device, a zero voltage current was observed. The critical current density (J_c) of the device was found to be dependent on the thickness of the barrier layer and the crystallinity of the a-axis oriented YBC electrodes. At 40 K, such a junction fabricated on a SrTiO₃ (100) substrate was found to have a J_c of 1.8 X 10⁴ A/cm² and an I_cR_n product of 0.2 mV.     

Gate tunable Rashba spin-orbit coupling at CaZrO3/SrTiO3 heterointerface

High mobility quasi two-dimensional electron gas (2DEG) found at the CaZrO₃/SrTiO₃ nonpolar heterointerface is attractive and provides a platform for the development of functional devices and nanoelectronics. Here we report that the carrier density and mobility at low temperature can be tuned by gate voltage at the CaZrO₃/SrTiO₃ interface. Furthermore, the magnitude of Rashba spin-orbit interaction can be modulated and increases with the gate voltage. Remarkably, the diffusion constant and the spin-orbit relaxation time can be strongly tuned by gate voltage. The diffusion constant increases by a factor of ～ 19.98 and the relaxation time is reduced by a factor of over three orders of magnitude while the gate voltage is swept from -50 V to 100 V. These findings not only lay a foundation for further understanding the underlying mechanism of Rashba spin-orbit coupling, but also have great significance in developing various oxide functional devices.     

Improving the device performances of two-dimensional semiconducting transition metal dichalcogenides: Three strategies

Two-dimensional (2D) semiconductors are emerging as promising candidates for the next-generation nanoelectronics. As a type of unique channel materials, 2D semiconducting transition metal dichalcogenides (TMDCs), such as MoS₂ and WS₂, exhibit great potential for the state-of-the-art field-effect transistors owing to their atomically thin thicknesses, dangling-band free surfaces, and abundant band structures. Even so, the device performances of 2D semiconducting TMDCs are still failing to reach the theoretical values so far, which is attributed to the intrinsic defects, excessive doping, and daunting contacts between electrodes and channels. In this article, we review the up-to-date three strategies for improving the device performances of 2D semiconducting TMDCs: (i) the controllable synthesis of wafer-scale 2D semiconducting TMDCs single crystals to reduce the evolution of grain boundaries, (ii) the ingenious doping of 2D semiconducting TMDCs to modulate the band structures and suppress the impurity scatterings, and (iii) the optimization design of interfacial contacts between electrodes and channels to reduce the Schottky barrier heights and contact resistances. In the end, the challenges regarding the improvement of device performances of 2D semiconducting TMDCs are highlighted, and the further research directions are also proposed. We believe that this review is comprehensive and insightful for downscaling the electronic devices and extending the Moore’s law.     

光电协同增强的场效应对LaAlO_3/SrTiO_3界面中持续光电导的调控

LaAlO_3/SrTiO_3异质结界面体系具有新奇的二维自由电子气现象、暂态光电导效应、持续光电导效应等丰富的光电性质,是近年来科学界研究的热点之一.本文研究了场效应对LaAlO_3/SrTiO_3界面光电导效应的调控,发现光电协同增强的场效应可以使得LaAlO_3/SrTiO_3界面产生显著的持续光电导效应,进一步研究发现:在光电协同效应的影响下,随着负的背栅门电压的增加,持续光电导的数值增大,在-70 V附近达到极值;随着负的背栅门电压处理时间的增加,持续光电导的数值单调增加.LaAlO_3/SrTiO_3异质结中这种场增强的持续光电导效应可为多参数可调的光电子记忆器件的研发提供参考依据.     

外电场辅助化学气相沉积方法制备网格状β-Ga2O3纳米线及其特性研究

利用外电场辅助化学气相沉积（CVD）方法,在蓝宝石衬底上制备出了由三组生长方向构成的网格状β-Ga₂O₃纳米线.研究了不同外加电压大小对β-Ga₂O₃纳米线表面形貌、晶体结构以及光学特性的影响.结果表明：外加电压的大小对样品的表面形貌有着非常大的影响,有外加电场作用时生长的β-Ga₂O₃纳米线取向性开始变好,只出现了由三组不同生长方向构成的网格状β-Ga₂O₃纳米线;并且随着外加电压的增加,纳米线分布变得更加密集、长度明显增长.此外,采用这种外电场辅助的CVD方法可以明显改善样品的结晶和光学质量.     

悬空氧化铟纳米线晶体管制备与光电性能表征

一维(1D)半导体纳米线在纳米电子学和纳米光子学中表现出色。然而,纳米线晶体管的电特性对纳米线与衬底之间的相互作用非常敏感,而优化器件结构可以改善纳米线晶体管的电学和光电检测性能。本文报道了通过一步式光刻技术制造的悬浮式In₂O₃纳米线晶体管,显示出54.6 cm²V^?1s^?1的高迁移率和241.5 mVdec^?1的低亚阈值摆幅。作为紫外光电探测器,光电晶体管显示出极低的暗电流(~10?13 A)和高响应度1.6×10⁵ A?W^?1。悬浮晶体管的沟道材料的这种简单而有效的制备方法可广泛用于制造高性能微纳米器件。     

U型槽刻蚀工艺对GaN垂直沟槽型金属-氧化物-半导体场效应晶体管电学特性的影响

U型槽的干法刻蚀工艺是GaN垂直沟槽型金属-氧化物-半导体场效应晶体管(MOSFET)器件关键的工艺步骤,干法刻蚀后GaN的侧壁状况直接影响GaN MOS结构中的界面态特性和器件的沟道电子输运.本文通过改变感应耦合等离子体干法刻蚀工艺中的射频功率和刻蚀掩模,研究了GaN垂直沟槽型MOSFET电学特性的工艺依赖性.研究结果表明,适当降低射频功率,在保证侧壁陡直的前提下可以改善沟道电子迁移率,从35.7 cm^2/(V·s)提高到48.1 cm^2/(V·s),并提高器件的工作电流.沟道处的界面态密度可以通过亚阈值摆幅提取,射频功率在50 W时界面态密度降低到1.90×10^12 cm^-2·eV^-1,比135 W条件下降低了一半.采用SiO2硬刻蚀掩模代替光刻胶掩模可以提高沟槽底部的刻蚀均匀性.较薄的SiO2掩模具有更小的侧壁面积,高能离子的反射作用更弱,过刻蚀现象明显改善,制备出的GaN垂直沟槽型MOSFET沟道场效应迁移率更高,界面态密度更低.     

High power-added-efficiency AlGaN/GaN HEMTs fabricated by atomic level controlled etching

An atomic-level controlled etching(ACE)technology is invstigated for the fabrication of recessed gate AlGaN/GaN high-electron-mobility transistors(HEMTs)with high power added efficiency.We compare the recessed gate HEMTs with conventional etching(CE)based chlorine,Cl₂-only ACE and BCl³/Cl₂ACE,respectively.The mixed radicals of BCl₃/Cl₂were used as the active reactants in the step of chemical modification.For ensuring precise and controllable etching depth and low etching damage,the kinetic energy of argon ions was accurately controlled.These argon ions were used precisely to remove the chemical modified surface atomic layer.Compared to the HEMTs with CE,the characteristics of devices fabricated by ACE are significantly improved,which benefits from significant reduction of etching damage.For BCl₃/Cl₂ACE recessed HEMTs,the load pull test at 17 GHz shows a high power added efficiency(PAE)of 59.8%with an output power density of 1.6 W/mm at Vd=10 V,and a peak PAE of 44.8%with an output power density of 3.2 W/mm at Vd=20 V in a continuous-wave mode.     

Investigation on threshold voltage of p-channel GaN MOSFETs based on p-GaN/AlGaN/GaN heterostructure

The threshold voltage (V_th) of the p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated via Silvaco-Atlas simulations. The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier height Φ_1,p, polarization charge density σ_b, and equivalent unite capacitance C_oc. It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V_th, and threshold voltage |V_th| increases with the reduction in p-GaN doping concentration and the work-function of gate metal. Meanwhile, the increase in gate dielectric relative permittivity may cause the increase in threshold voltage |V_th|. Additionally, the parameter influencing output current most is the p-GaN doping concentration, and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5×10¹⁶ cm^-3 at V_GS = -12 V and V_DS = -10 V.