FPGA-based amplitude and phase detection in DLLRF

The new generation particle accelerator requires a highly stable radio frequency（RF） system. The stability of the RF system is realized by the Low Level RF（LLRF） subsystem which controls the amplitude and phase of the RF signal. The detection of the RF signal＇s amplitude and phase is fundamental to LLRF controls. High-speed ADC（Analog to Digital Converter） ,DAC（Digital to Analog Converter） and FPGA（Field Programmable Gate Array） play very important roles in digital LLRF control systems. This paper describes the implementation of real-time amplitude and phase detection based of the FPGA with an analysis of the main factors that affect the detection accuracy such as jitter,algorithm＇s defects and non-linearity of devices,which is helpful for future work on high precision detection and control.     

A digital low-level radio-frequency system R&D for a 1.3 GHz nine-cell cavity

To test and verify the performance of the digital low-level radio-frequency (LLRF) and tuner system designed by the IHEP RF group, an experimental platform with a retired KEK 1.3 GHz nine-cell cavity is set up. A radio-frequency (RF) field is established successfully in the cavity and the frequency of the cavity is locked by the tuner in ±0.5° (about ±1.2 kHz) at room temperature. The digital LLRF system performs well in a five-hour experiment, and the results show that the system achieves field stability at amplitude <0.1% (peak to peak) and phase <0.1° (peak to peak). This index satisfies the requirements of the International Linear Collider (ILC), and this paper describes this closed-loop experiment of the LLRF system.     

Design of a low level radio frequency control system for the direct current-superconductive photocathode injector at Peking University

A digital low level radio frequency (LLRF) control system based on a high precision field-programmable gate array (FPGA) is being developed for the stable operation of the upgraded direct current-superconductive (DC-SC) photocathode injector at Peking University. The design of this LLRF control system is described, including both the hardware and the internal algorithm. Analysis of disturbances shows that the system can achieve the requirement of ±0.1% for amplitude stability and ±0.1° for phase stability. Through experiments, preliminary results are presented in the paper.     

High accuracy amplitude and phase measurements based on a double heterodyne architecture

In the digital low level RF (LLRF) system of a circular (particle) accelerator, the RF field signal is usually down converted to a fixed intermediate frequency (IF). The ratio of IF and sampling frequency determines the processing required, and differs in various LLRF systems. It is generally desirable to design a universally compatible architecture for different IFs with no change to the sampling frequency and algorithm. A new RF detection method based on a double heterodyne architecture for wide IF range has been developed, which achieves the high accuracy requirement of modern LLRF. In this paper, the relation of IF and phase error is systematically analyzed for the first time and verified by experiments. The effects of temperature drift for 16 h IF detection are inhibited by the amplitude and phase calibrations.     

R&D of an LLRF control system for a 162.5 MHz radio frequency system

This paper describes a low level radio frequency control system that was developed by the Institute of Modern Physics Chinese Academy of Sciences, and will be used in Injector of the China-ADS project. The LLRF control system consists of an RF modulated front end, fast analog-to-digital converter (ADC) modules, and a digital signal processing board based on a field programmable gate array. The system has been tested on a room temperature cavity with 12-hr, and the results illustrate that the stability of amplitude and phase achieved ±0.32% and ±0.35 degrees, respectively.     

HIRFL 高频相位与幅度稳定系统

介绍了兰州重离子研究装置(HIRFL) 主回旋加速器(SSC) 高频系统高频电压的相位稳定与幅度稳定系统,重点介绍了设备的组成和稳定环路设计以及正交变换与稳定环路滤波器的设计方法。通过在SSC 腔体上进行的长期的现场测试,得到了调制抑制度与长期稳定度的测试方法,并对结果进行了分析。其中,设备的长期相位稳定度达到0:014°,长期幅度稳定度达到1.29x10-4,远高于改造前的指标。The phase and amplitude stabilization system of high-frequency voltage on the main cyclotron SSC of Heavy Ion Research Facility in Lanzhou (HIRFL) is introduced. The system composition, negative feedback loop design and other important aspects about the development of the system are particularly presented in this paper. Designing method of digital PLL orthogonal transformation and loop filter of phase and amplitude stabilization are introduced in detail. Control systems of SSC have been tested through a long-term stability experiments, the test method of the parasitic modulation suppression and stabilization in long term is proposed. According to the analyzing data, it shows that phase control accuracy in long term is within 0:014° and the amplitude deviation in long term is lower than 1.29x10-4. Compared with the traditional system, its capability and target is much better.     

Design and performance of the LLRF system for CSNS/RCS

The rapid cycling synchrotron(RCS) is part of the China Spallation Neutron Source(CSNS). The RCS provides 1.6 Ge V protons with a repetition rate of 25 Hz. The RF system in RCS is mainly composed of a ferrite loaded RF cavity, a high power tetrode amplifier, a bias supply of 3300 A and a digital low level RF(LLRF) system based on FPGA. The major challenge of the LLRF system is to solve problems caused by rapid frequency sweeping and the heavy beam loading effect. A total of eight control loops are applied to ensure the normal operation. An effective feedforward scheme is widely used to improve the dynamic performance of the system. The design of the LLRF system and high power integration test results with the prototype RF system are presented.     

Phase-dependent inversionless gain in a four-level atomic system with a closed interaction loop

A four-level atomic system with a closed interaction loop connected by two coherent driving fields and a microwave field is investigated. The results show that inversionless gain can be achieved on a higher frequency transition outside the closed interaction loop, and the gain behaviour can be modulated by the phase of the closed loop as well as the amplitude of the microwave field. The phase sensitivity property in such a scheme is similar to that in an analogous configuration with spontaneously generated coherence, but it is beyond the rigorous condition of near-degenerate levels with non-orthogonal dipole moments. Therefore this scheme is much more convenient in experimental realization.     

Digital prototype of LLRF system for SSRF

This paper describes a field programming gate array (FPGA) based low level radio frequency (LLRF) prototype for the SSRF storage ring RF system. This prototype includes the local oscillator (LO), analog front end, digital front end, RF out, clock distributing, digital signal processing and communication functions. All feedback algorithms are performed in FPGA. The long term of the test prototype with high power shows that the variations of the RF amplitude and the phase in the accelerating cavity are less than 1% and 1° respectively, and the variation of the cavity resonance frequency is controlled within ±10 Hz.     

干涉成像系统传递函数的数值分析

干涉仪系统传递函数能有效地表征系统相位成像的性能。通过假设干涉成像系统是复振幅的线性平移不变系统,模拟计算正弦相位光栅和相位台阶这两类标准相位物体的成像,确定干涉仪系统传递函数。数值分析结果表明:系统传递函数随着波像差的增加而减小;干涉成像系统对小幅度相位（远小于1 rad）成像是近似线性的,而对大幅度相位(大于0.5 rad）成像则是明显非线性的。当正弦相位的幅度为1时,系统传递函数在1/2和1/3截止频率处出现明显的急剧下降。高度为/2的相位台阶成像时,系统传递函数随着空间频率的增加而缓慢地降低。 The performance of phase imaging in interferometric imaging system is well characterized by the system transfer function (STF). The STF of the interferometric imaging system is analyzed numerically by assuming that the system is linear and shift-invariant for the complex field. Two standard phase objects, sinusoidal phase grating and phase step, are employed and simulated to determine the STF. Numerical simulation results show that the STF decreases as the wavefront aberration of interferometric imaging system increases. It also shows that the interferometric imaging system is approximately linear for small phase (far less than 1 rad) but explicitly nonlinear for large phase (larger than 0.5 rad). The STF has a visible drop at one half or one third of the cut-off frequency of the imaging system when the amplitude of sinusoidal phase is 1 rad. For a phase step with a height of /2 rad, the STF has no visible drop but decreases slowly with the increasing of spatial frequency. The results provide a useful guidance to the design of interferometer and the measurement of STF and power spectrum density in experiment.     

FPGA-based amplitude and phase detection in DLLRF

The new generation particle accelerator requires a highly stable radio frequency (RF) system. The stability of the RF system is realized by the Low Level RF (LLRF) subsystem which controls the amplitude and phase of the RF signal. The detection of the RF signal's amplitude and phase is fundamental to LLRF controls. High-speed ADC (Analog to Digital Converter), DAC (Digital to Analog Converter) and FPGA (Field Programmable Gate Array) play very important roles in digital LLRF control systems. This paper describes the implementation of real-time amplitude and phase detection based of the FPGA with an analysis of the main factors that affect the detection accuracy such as jitter, algorithm's defects and non-linearity of devices, which is helpful for future work on high precision detection and control.     

强流质子RFQ加速器高频数字低电平控制系统

强流质子RFQ加速器加速场的频率为352.2 MHz,加速场幅度和相位的精度分别要求控制在±1%和±1°的范围,为了达到这一要求,设计了一套数字低电平控制系统,该系统包括加速场的幅度和相位控制、腔体的谐振频率控制和高功率射频连锁保护3个部分。腔体采样信号的下变频及反馈激励信号的上变频由模拟器件来完成。幅相实时反馈处理过程采用数字I/Q解调的方法,在1块stratixⅡ的FPGA板上实现,板上另有3块DSP用于通信和协助FPGA进行数据处理。系统完成后与RFQ加速器进行联机调试,测试结果基本满足控制精度的要求。     

100MeV强流回旋加速器射频数字低电平系统研制

介绍了100MeV射频低电平控制系统的设计及其桌面实验的组成. 通过实测, 验证了他激模式下幅度控制环路和相位控制环路中实现数字式控制的可行性. 初步测试数据及调试过程均表明数字式控制可用于100MeV回旋加速器的射频低电平控制系统.     

R&D of an LLRF control system for a 162.5 MHz radio frequency system

This paper describes a low level radio frequency control system that was developed by the Institute of Modern Physics Chinese Academy of Sciences, and will be used in Injector Ⅱ of the China-ADS project. The LLRF control system consists of an RF modulated front end, fast analog-to-digital converter (ADC) modules, and a digital signal processing board based on a field programmable gate array. The system has been tested on a room temperature cavity with 12-hr, and the results illustrate that the stability of amplitude and phase achieved ± 0.32% and ± 0.35 degrees, respectively.     

CSNS LINAC低电平射频控制系统软件设计

低电平射频控制系统主要用于对加速腔的高频场和谐振频率的控制,保证加速器的稳定运行并输出高品质的束流.低电平控制系统软件提供可视化操作界面,实现数据显示和存储、自动化算法等功能,提高了低电平系统的可操作性,减少了人工作业量和故障率.软件开发具有灵活性强、开发周期短的特点,适合控制速度要求相对不高而逻辑较为复杂的功能开发....     

Digital prototype of LLRF system for SSRF

This paper describes a field programming gate array(FPGA)based low level radio frequency (LLRF)prototype for the SSRF storage ring RF system.This prototype includes the local oscillator(LO),analog front end,digital front end,RF out,clock distributing,digital signal processing and communication functions.All feedback algorithms are performed in FPGA.The long term of the test prototype with high power shows that the variations of the RF amplitude and the phase in the accelerating cavity are less than 1%and 1°respectively.and the variation of the cavity resonance frequency is controlled within ±10 Hz.     

快循环同步加速器射频加速电压幅度的数字化控制

 中国散裂中子源(CSNS)快循环同步加速器（RCS）中的射频低电平控制系统是基于FPGA的全数字控制系统,旨在完成对射频频率、加速电压和同步加速相位的控制。介绍了CSNS/RCS射频系统的低电平数字化控制设计方案,并着重对射频加速电压幅度控制回路进行了分析与讨论。电压幅度控制环路通过射频电压幅度信号与电压幅度设定值的比较,得到误差信号。误差信号经过控制器来控制输入到射频腔的功率,以达到稳定和改变腔压的目的。通过对控制对象的分析和建模,得到了满足系统要求的控制器。详细介绍了数字系统的实现,尤其是信号的解调和控制算法的实现。用ALTERA公司的DSP builder进行数字控制系统开发,系统仿真结果表明,环路误差信号大约于10 μs（400个系统时钟）后归于0,整个电压幅度控制环路能稳定运行。     

Design and evaluation of a downconverter based on MicroTCA.4

Modern low-level RF(LLRF) control systems of particle accelerators are designed to achieve extremely precise field amplitude and phase regulation inside the accelerating cavities. The RF field signal is usually converted to an intermediate frequency(IF) before being sampled by ADC. As the down-conversion is an important procedure of digital signal processing in LLRF system, designing a high performance and broad band downconverter compatible with various accelerators is important. In this paper, the design of a downconverter based on Micro TCA and its performance evaluation on different frequency points are presented. The major design objective of this module is a wider operating frequency range and more flexibility in application.