次谐波聚束系统固态放大器相位特性

 为研究BEPCⅡ直线加速器次谐波聚束系统使用的两台固态放大器（20 kW/142.8 MHz,10 kW/571.2 MHz）的相位特性,利用基于现场可编程门阵列(FPGA)的数字测量方法对两台固态放大器的脉内相移和相位稳定度进行了测量。测量系统硬件包括频率综合器、FPGA数字信号处理板和PC;软件部分包括FPGA内部算法、通信及PC端界面程序。该测量系统能真实地反映两台固态放大器的相位特性,为次谐波聚束器的相位补偿提供了参考。     

ADS注入器Ⅰ高频四极场功率源系统研制

ADS注入器Ⅰ高频四极场(RFQ)功率源系统将为325MHz RFQ提供连续波功率,使束流离开RFQ时,其能量达到几MeV。功率源系统除了补偿RFQ腔耗外,还必须提供足够的功率以保证RFQ中的加速电场。ADS注入器ⅠRFQ功率源系统主要包括600kW连续波速调管、80kV/18A基于脉冲步进调制技术的PSM电源、环流器以及相应的波导传输系统等。根据ADS总体指标和RFQ的相关技术参数,提出了功率源的总体布局、技术指标以及设计要求等,在此基础上完成系统安装与调试,并通过专家组测试与验收。     

BEPCⅡ高频系统的建造

北京正负电子对撞机二期(BEPCⅡ)的高频系统已于2006年11月投入运行,它包括了3个子系统:超导腔、发射机和低电平控制系统.与以前的高频系统相比,工作频率由200MHz变为499.8MHz,超导腔取代了常温腔.在过去一年的运行中,高频系统表现良好,达到了设计指标.     

BEPCⅡ零模束流反馈系统研制

 为了抑制BEPCⅡ多束团(93团)、大流强（910 mA）时的纵向振荡（零模）,引入了BEPCⅡ零模束流反馈系统。该系统首次应用于BEPCⅡ储存环上,它包括了束流信号采集、滤波、下变频、鉴相、移相等几个部分。使用该系统后,束流的纵向边带被抑制度大于10 dB,这表明,系统能够抑制束流的纵向振荡。     

BEPCⅡ高频系统的建造

北京正负电子对撞机二期(BEPCⅡ)的高频系统已于2006年11月投入运行, 它包括了3个子系统:     

Progress on the construction of the 100 MeV/100 kW electron linac for the NSC KIPT neutron source

IHEP, China is constructing a 100 MeV/100 kW electron Linac for NSC KIPT, Ukraine. This linac will be used as the driver of a neutron source based on a subcritical assembly. In 2012, the injector part of the accelerator was pre-installed as a testing facility in the experimental hall #2 of IHEP. The injector beam and key hardware testing results met the design goal. Recently, the injector testing facility was disassembled and all of the components for the whole accelerator have been shipped to Ukraine from China by the ocean shipping. The installation of the whole machine in KIPT will be started in June, 2013. The construction progress, the design and testing results of the injector beam and key hardware are presented.     

A digital low-level radio-frequency system R&D for a 1.3 GHz nine-cell cavity

To test and verify the performance of the digital low-level radio-frequency (LLRF) and tuner system designed by the IHEP RF group, an experimental platform with a retired KEK 1.3 GHz nine-cell cavity is set up. A radio-frequency (RF) field is established successfully in the cavity and the frequency of the cavity is locked by the tuner in ±0.5° (about ±1.2 kHz) at room temperature. The digital LLRF system performs well in a five-hour experiment, and the results show that the system achieves field stability at amplitude <0.1% (peak to peak) and phase <0.1° (peak to peak). This index satisfies the requirements of the International Linear Collider (ILC), and this paper describes this closed-loop experiment of the LLRF system.     

FPGA-based amplitude and phase detection in DLLRF

The new generation particle accelerator requires a highly stable radio frequency（RF） system. The stability of the RF system is realized by the Low Level RF（LLRF） subsystem which controls the amplitude and phase of the RF signal. The detection of the RF signal＇s amplitude and phase is fundamental to LLRF controls. High-speed ADC（Analog to Digital Converter） ,DAC（Digital to Analog Converter） and FPGA（Field Programmable Gate Array） play very important roles in digital LLRF control systems. This paper describes the implementation of real-time amplitude and phase detection based of the FPGA with an analysis of the main factors that affect the detection accuracy such as jitter,algorithm＇s defects and non-linearity of devices,which is helpful for future work on high precision detection and control.