Development of a prototype of the ME readout electronics onboard the HXMT satellite

A prototype of the ME readout electronics onboard the Hard X-ray Modulate Telescope （HXMT） satellite is developed. Application Specific Integrated Chip （ASIC） is used to construct the front end electronics due to a large number of detectors. Field Programmable Gate Array （FPGA） is connected to the ASIC as a state machine controller and data FIFO in the DAQ system. A USB board is designed to communicate between the DAQ system and the computer. The design goals and features, the operation of the system and the preliminary performance of the prototype are described. The testing results show that the design goals of the prototype system have been achieved.     

HIRFL-CSR外靶实验T0探测器前端电子学原型模块设计

介绍了兰州重离子加速器冷却储存环（HIRFL-CSR）外靶实验中时间起点探测器（T0）的前端电子学原型模块的设计与测试。探索了基于过阈时间法和专用集成电路NINO芯片进行多气隙电阻板室探测器信号读出的模拟前端电路的设计技术,并实际完成了原型电子学模块的设计。此模块共集成6个测量通道,可以进行前沿甄别及电荷时间变换。目前已经在实验室条件下完成了各项电子学性能测试,包括不同甄别阈值下的时间精度测试以及不同输入信号幅度下的输出脉宽测试。测试结果表明,在100 fC至2 pC的动态范围内,此模块时间精度好于20 ps,满足应用需求,这也为进一步的电子学系统设计做好了准备。A prototype front end electronics (FEE) module is designed for the T0 detector in the External Experiment in CSR (Cooling Storage Ring) of HIRFL (Heavy Ion Research Facility in Lanzhou). Based on the Time-Over-Threshold method and NINO ASIC, a total of 6 channels are integrated in the module, and both high precision leading edge discrimination and Charge-to-Time Conversion can be achieved, which satisfies the readout requirement of MRPC (Multi-gap Resistive Plate Chamber). A series of tests were also conducted in the laboratory, including time precision tests with different thresholds and output pulse width tests with different input signal amplitudes. Test results indicate that this prototype module functions well, and the time precision is better than 20 ps in the dynamic range from 100 fC to 2 pC, which is beyond application requirement. Through this work, preparation is made for the future readout system design.     

基于SCA ASIC的高精度时间测量原型电子学设计

基于高速波形数字化实现高精度时间测量是核与粒子物理实验读出电子学中的研究热点。本工作针对高精度时间测量的需求基于实验室自主研发的开关电容阵列(Switched Capacitor Array, SCA)专用集成电路(Application Specific Integrated Circuit,ASIC)开展16通道集成的时间测量电子学原型的设计,输入信号经过SCA采样和量化后传输至现场可编程逻辑阵列(Field Programmable Gate Array, FPGA),在FPGA中进行误差修正、时间内插和数字甄别提取出时间信息。目前已在实验室环境下完成此电子学的时间精度测试,测试结果表明,此电子学可以实现好于10 ps RMS(Root Mean Square)的时间精度。     

Interface design in nanosystems of Advanced Superionic Conductors

First attempt of practical realization of new interface engineering approach “from advanced materials to advanced devices” for nanosystems of Advanced Superionic Conductors (ASICs), based on AgI (CuI) compounds is presented. Crystallochemical method of symmetry perfect ASIC//electrode interface searching is developed. Some new theoretical results of ASIC//indifferent electrode conjugated commensurate heteropairs with coherent interfaces and preliminary experimental results of the creation of thin-film supercapacitor — prototype based on the lattice matched heterojunction — are given. Future perspectives of the ASIC//electrode interface design suited for micro(nano)electronics and microsystem technology (MST) are discussed. Paper presented at the Patras Conference on Solid State Ionics — Transport Properties, Patras, Greece, Sept. 14–18, 2004.     

Prototype of time digitizing system for BESⅢ endcap TOF upgrade

The prototype of a time digitizing system for the BESⅢ endcap TOF (ETOF) upgrade is introduced in this paper. The ETOF readout electronics has a distributed architecture. Hit signals from the multi-gap resistive plate chamber (MRPC) are signaled as LVDS by front-end electronics (FEE) and are then sent to the back-end time digitizing system via long shield differential twisted pair cables. The ETOF digitizing system consists of two VME crates, each of which contains modules for time digitization, clock, trigger, fast control, etc. The time digitizing module (TDIG) of this prototype can support up to 72 electrical channels for hit information measurement. The fast control (FCTL) module can operate in barrel or endcap mode. The barrel FCTL fans out fast control signals from the trigger system to the endcap FCTLs, merges data from the endcaps and then transfers to the trigger system. Without modifying the barrel TOF (BTOF) structure, this time digitizing architecture benefits from improved ETOF performance without degrading the BTOF performance. Lab experiments show that the time resolution of this digitizing system can be lower than 20 ps, and the data throughput to the DAQ can be about 92 Mbps. Beam experiments show that the total time resolution can be lower than 45 ps.     

Prototype of time digitizing system for BESⅢ endcap TOF upgrade

The prototype of a time digitizing system for the BESⅢ endcap TOF (ETOF) upgrade is introduced in this paper. The ETOF readout electronics has a distributed architecture. Hit signals from the multi-gap resistive plate chamber (MRPC) are signaled as LVDS by front-end electronics (FEE) and are then sent to the back-end time digitizing system via long shield differential twisted pair cables. The ETOF digitizing system consists of two VME crates, each of which contains modules for time digitization, clock, trigger, fast control, etc. The time digitizing module (TDIG) of this prototype can support up to 72 electrical channels for hit information measurement. The fast control (FCTL) module can operate in barrel or endcap mode. The barrel FCTL fans out fast control signals from the trigger system to the endcap FCTLs, merges data from the endcaps and then transfers to the trigger system. Without modifying the barrel TOF (BTOF) structure, this time digitizing architecture benefits from improved ETOF performance without degrading the BTOF performance. Lab experiments show that the time resolution of this digitizing system can be lower than 20 ps, and the data throughput to the DAQ can be about 92 Mbps. Beam experiments show that the total time resolution can be lower than 45 ps.     

India-based Neutrino Observatory

The current status of the India-based Neutrino Observatory (INO) is summarized. The main physics goals are described followed by the motivation for building a magnetized iron calorimetric?(ICAL) detector. The charge identification capability of ICAL would make it complementary to large water Cerenkov and other detectors worldwide. The status of the design of the 50 kt magnet, the construction of a prototype ICAL detector, the experience with resistive plate chambers which will be the active elements in ICAL and the status of the associated electronics and data acquisition system are discussed.     

A data transmission method for particle physics experiments based on Ethernet physical layer

Due to its advantages of universality, flexibility and high performance, fast Ethernet is widely used in readout system design for modern particle physics experiments. However, Ethernet is usually used together with the TCP/IP protocol stack, which makes it difficult to implement readout systems because designers have to use the operating system to process this protocol. Furthermore, TCP/IP degrades the transmission efficiency and real-time performance. To maximize the performance of Ethernet in physics experiment applications, a data readout method based on the physical layer(PHY) is proposed. In this method, TCP/IP is replaced with a customized and simple protocol, which makes it easier to implement. On each readout module, data from the front-end electronics is first fed into an FPGA for protocol processing and then sent out to a PHY chip controlled by this FPGA for transmission.This kind of data path is fully implemented by hardware. From the side of the data acquisition system(DAQ),however, the absence of a standard protocol causes problems for the network related applications. To solve this problem, in the operating system kernel space, data received by the network interface card is redirected from the traditional flow to a specified memory space by a customized program. This memory space can easily be accessed by applications in user space. For the purpose of verification, a prototype system has been designed and implemented.Preliminary test results show that this method can meet the requirements of data transmission from the readout module to the DAQ with an efficient and simple manner.     

2维位置灵敏中子探测器读出

 介绍了基于厚型气体电子倍增探测器(THGEM)的位置灵敏热中子探测器中,采用专用集成电路的阵列电荷灵敏前置放大和可编程器件的读出电子学设计。专用集成电路采用VA64TA2,64通道输入电荷灵敏放大成型,触发输出。控制电路使用了现场可编程器件。两者结合,显著减少了读出电路在探测器内所占据的空间。介绍了VA64TA2裸片的封装,给出了电路的原理和时序,进行了线性和电子学噪声试验,结果表明电路具有16 fC的线性动态范围,电子学噪声仅为75个电子电荷。     

12 bit 30 MSPS逐次比较型ADC的测试

针对物理实验读出的需求设计了一款低功耗12 bit 30 MSPS逐次比较型模数变换器（Analog-to-Digital Converter,ADC）芯片,为评估其性能指标参数,需进行系统的测试。在本研究工作中构建了测试系统,然后按照IEEE标准进行了系统的测试和分析。测试结果表明,输入信号在基带范围内ADC有效位（Effective Number Of Bit,ENOB）约为9 bit,达到了本版本芯片的设计指标。同时,综合分析静态性能与动态性能测试结果,可以通过优化逐次比较型ADC中电容阵列电容失配参数,进一步提升ADC的非线性指标,为下一版芯片的改进设计提供了参考依据。Aiming at the requirement of readout electronics in physics experiments, a 12 bit 30 MSPS successiveapproximation-register (SAR) analog-to-digital converter (ADC) with low power consumption has been designed. To evaluate the performance of this ASIC, we conducted a series of tests. We set up a test system, and we tested the ADC according to IEEE std 1241-2010. The test results indicate that the effective number of bit (ENOB) of the ADC is around 9 bits when the input signal is in the first Nyquist zone, which has met the design requirements. According to the results of dynamic and static tests of this ADC, we found that the non-linearity performance of this ASIC can be further enhanced by improving the mismatching among the capacitor array, and this provides important information for the design of the second version of this ADC.     

CSNS多功能反射谱仪3He管探测器数据获取系统设计

作为中国散裂中子源(CSNS)工程中多功能反射(RM)谱仪一部分的3He管探测器数据获取系统不仅要具有基本的读取和处理数据的功能,还需要协调配合谱仪的整体运行,稳定可靠地与其它异构系统进行交互。通过规划数据获取的整体框架,采取有效的方式优化关键部分,另外挑选合适的三方软件包整合到数据获取系统中,达到了该系统操作方便灵活、功能完善、运行稳定可靠并且高效率,满足谱仪实验需求的目的。包括数据获取系统在内的多功能反射谱仪顺利通过了国家验收,目前这套数据获取系统已经成功应用在多功能反射谱仪的束流实验中。     

用于SCA ASIC测试的数字读出模块设计

高速开关电容阵列(SCA)具有高速采样、低功耗的特点,基于SCA的高速波形数字化是目前高精度时间测量的一个重要研究方向。为此,我们开展SCA芯片的研究,目前已设计完成原型ASIC设计,并正在进行后续版本的改进设计。为便于未来多版本ASIC的测试和评估,需设计具有一定通用性的数字读出模块,本论文工作主要介绍此模块的设计工作以及相应的数据读出软件。数字读出模块基于FPGA实现对待测ASIC的控制、配置及数据读出,采用DDR3片外存储芯片,使用USB3.0等接口进行数据传输;上位机软件基于Python3.7设计,实现了数据采集与波形绘制等功能。目前已使用设计完成的数字读出模块对第2版SCA ASIC进行了初步的测试,测试结果表明,此读出模块工作正常,且SCA芯片输出结果符合预期。     

Very forward calorimeters readout and machine interface

The paper describes the requirements for the readout electronics and DAQ for the instrumentation of the forward region of the future detector at the international linear collider. The preliminary design is discussed. on behalf of the FCAL Collaboration     

A Simple X-ray Spectrometer and PC-based Data Acquisition System for Newly Developed X-ray Source Based on Laser Compton Scattering

A simple X-ray spectrometer and a PC-Based Data Acquisition System(DAS) have been developed newly in Shanghai Institute of Applied Physics(SINAP),Chinese Academy of Sciences (CAS) for the measurement of the X-ray source generated using laser Compton scattering.The system consists of liquid nitrogen cooled high resolution Si(Li) detector,electronics and a DAQ.The Si(Li) detector was designed and made by Center of Advanced Instruments in SINAP,CAS,it allows us to measure X-rays with the energy up to 60 keV and the energy resolution(FWHM) of 184 eV at 5.9 keV.We measured the system uncertainty was 0.2 eV and time drifting of detector was 0.05% both at 5.9 keV.The DAQ was based on Object-Oriented software LabVIEW 7.1,it has data on-line analysis and original data saved functions.     

High resolution solar soft X-ray spectrometer

A high resolution solar soft X-ray spectrometer (SOX) payload onboard a satellite is developed. A silicon drift detector (SDD) is adopted as the detector of the SOX spectrometer. The spectrometer consists of the detectors and their readout electronics, a data acquisition unit and a payload data handling unit. A ground test system is also developed to test SOX. The test results show that the design goals of the spectrometer system have been achieved.     

LHAASO WCDA前端芯片批量测试系统的设计

LHAASO(Large High Altitude Air Shower Observatory)WCDA(Water Cerenkov Detector Array)要求其读出电子学实现大动态范围下精确的时间和电荷测量，为此设计了一款前端读出芯片PASC(Pre-Amplifier and Shaping Circuit) ASIC(Application Specific Integrated Circuit)，即将用于LHAASO WCDA第三水池的读出。为了满足对此芯片大批量测试需求，设计了此ASIC测试系统，实现了对芯片时间和电荷性能的自动化测试。在介绍此芯片基本工作原理的基础上，讨论了测试系统的设计方案和基本结构，包括硬件电路设计和自动化测试软件设计。该测试系统已应用于LHAASO工程项目的芯片筛选并且已完成了100片芯片的测试工作，能够通过中央控制软件，与多台仪器通讯，进行仪器控制，完成自动化测试和数据记录。这一自动化测试方法，更适用于大动态范围下、高精度读出芯片的性能测试和评估，大大简化测试流程，尤其能够大幅提升批量测试中大量重复性测试步骤的工作效率。文中展示了基于此测试系统已完成的100片芯片的测试结果，结果表明，芯片各项性能参数满足LHAASO第三水池工程应用需求。     

用于像素探测器的高事例率高精度TDC ASIC原型电路的设计与仿真

像素探测器因其优异的位置分辨能力在高能粒子物理实验的内径探测器中有着广泛应用,随着应用场景的发展,许多物理实验要求探测器及其读出电子学也具备高精度时间测量的能力。针对像素探测器时间测量的需求,设计完成了一款具备高事例率处理能力、高精度特点的TDC(Time-to-Digital Conversion) ASIC(Application Specific Integrated Circuit) 原型电路,将来可以作为核心组成部分集成到像素探测器前端读出ASIC中。采用粗细结合的方案完成TDC的设计,其中粗时间测量基于计数器实现,细时间测量采用TAC(Time-to-Amplitude Converter)结合ADC(Time-to-Amplitude Converter)的结构实现,基于130 nm工艺完成了原型电路的设计。对TDC进行仿真,仿真结果表明,该电路可以最多处理连续11个事例,相邻事例的最短时间间隔为500 ps,bin size达到了2 ps,DNL(Differential Non-Linearity)小于2.8 ps,时间测量精度好于5 ps RMS。     

Images of triple gas electron multiplier with pixel-pads

Testing of a triple gas electron multiplier (GEM) with pixel-pads is described. Images by scanning and suspending radioactive sources were obtained by using 96 channels digital data acquisition (DAQ) system which was composed of 96 8× 8~mm² pads and associated electronics channels.     

A Flash-ADC data acquisition system developed for a drift chamber array and a digital filter algorithm for signal processing

A Flash-ADC data acquisition (DAQ) system has been developed for the drift chamber array designed for the External-Target-Experiment at the Cooling Storage Ring at the Heavy Ion Research Facility, Lanzhou. The simplified readout electronics system has been developed using the Flash-ADC modules and the whole waveform in the sampling window is obtained, with which the time and energy information can be deduced with an offline processing. A digital filter algorithm has been developed to discriminate the noise and the useful signal. With the digital filtering process, the signal to noise ratio (SNR) is increased and a better time and energy resolution can be obtained.     

塑料闪烁体阵列探测器读出ASIC中峰值保持电路的设计

塑料闪烁体阵列探测器(PSD,简称塑闪阵列探测器)的输出信号经过前置放大器和滤波成形电路后输出准高斯波形,利用峰值保持电路可对准高斯波形信号的峰值进行采样和保持,以便后续的电子学系统对其进行进一步的分析。本工作采用180 nm CMOS工艺设计并实现了一款峰值保持电路ASIC芯片,每通道主要由跨导放大器(OTA)、电流镜和充电电容三部分电路组成。实验室电子学功能和性能测试结果表明:峰值保持电路功能良好;输入动态范围为33~940 mV,非线性误差优于0.8%,下垂速率好于8.6 μV/μs,峰值探测延迟时间小于35 ns,芯片单通道静态功耗为825 μW,达到设计要求。