远紫外光子计数成像探测器的感应电荷读出方法

为了满足空间远紫外波段成像高空间分辨率和高计数率的探测需求,阐述了光子计数成像探测器的感应电荷读出方法,用于对地球电离层进行远紫外波段遥感探测的成像光谱仪.研究了具有成形网路的电荷灵敏放大器各参数间的关系,从理论上分析了电荷灵敏放大器的上升时间及成形网络的成形时间常数对电荷读出噪声和探测系统计数率的影响,并建立了它们之间的定量关系.提出了电荷读出网络参数的设计和选取原则,并采用适合空间环境的分立电子元件研制出基于楔条形阳极光子计数式成像探测器的电荷读出电路.实验结果表明,所设计的感应电荷读取链路在成形时间为500 ns时链路等效输入噪声电荷约为230 e,电荷灵敏放大器上升时间小于8 ns,与建立的模型计算值有较好的一致性.在入射光强计数率86.2 kcps条件下,所测图像的空间分辨率达到7.13 lp/mm,满足空间远紫外波段成像光谱仪的使用要求.     

基于读出条读出的二维位置灵敏气体电子倍增器的研制

为研发能够满足北京同步辐射(BSRF)实验要求的二维探测器,研制了基于读出条读出的二维位置灵敏X射线气体电子倍增器(GEM).实验过程中通过改进读出条的周期,并基于中科院高能所实验物理中心电子学组研制的多路电荷放大器系统与VME存储-ADC系统,对软X射线源的位置分辨率进行了精密测量且得到了优异的二维位置分辨:X方向约为84μm,Y方向约为75μm.研究了三级GEM压差之和对位置分辨的影响,并测试了探测器的位置准确度与线性.对基于阳极读出的GEM用于模拟读出测试系统得到了一定的理论认识,侧重研究了GEM探测器基于模拟读出的系统特性,给出了相关的分析与讨论.     

高时间分辨MRPC的位置灵敏读出方法

根据MRPC工作机制和高时间分辨的特性, 研制一种位置灵敏MRPC原型及读出方法. 该探测器具有10个220μm气隙, 有效探测面积为20cm×20cm. 前端电子学采用专用ASIC芯片, 具有快时间响应和输入电荷-输出信号宽度的转换功能. 采取同时读取信号传输时间差和感应信号分布的方法实现两维读出. 对该探测器性能的束流测试结果显示: 沿着读出条方向及其垂直方向的位置分辨分别为4.5mm和1.6mm, 其时间分辨达到63ps, 探测效率>95%.     

基于光纤传感的核信号读出方法中的调制驱动模块设计和实现

基于光相位调制的核信号读出方法将探测器信号调制进光纤中，并使用光纤作为模拟信号的传输介质。在该读出方案中，调制驱动模块负责载波信号的产生及放大，是该方案读出电子学系统的重要组成部分。为了产生低相位噪声，幅度大且幅度可调的载波信号，本工作提出了基于锁相环的载波产生电路和基于MMIC射频放大器的载波放大电路的设计方案，该方案结构简单，尺寸小，性能优异。对载波产生电路使用了ADIsimPLL仿真软件进行了环路滤波器的设计和仿真，同时也对载波放大电路使用ADS仿真软件进行了设计和仿真，并在实验室条件下进行了测试。测试结果表明，输出26 dBm载波信号相位噪声好于–110 dBc/Hz@100 kHz，能够用于信号解调。     

Research on front-end electronics gain compensation of MCP imaging detector北大核心CSCD

基于微通道板电子倍增电荷分割型阳极的成像探测器常用于行星大气、气辉等微弱信号探测。针对探测器读出电路增益不相等导致探测器成像产生畸变的问题,利用理论分析结合MATLAB仿真揭示了不同畸变图像的形成机制,在该基础上提出了一种探测器读出电路增益补偿方法减小探测器成像畸变。通过MATLAB仿真和实验测试结果表明该文提出的方法能够有效减小由于读出电路增益不相等导致的探测器成像畸变。     

HT-7������ķѷɢ���źŴ����·���

为了检测到散射信号且有较高的信噪比,使用硅雪崩二极管(APD)探测器探测汤姆逊散射光,采用电荷敏感运算放大器减小电子噪声。同时,设计了放大电路,并采取了一些抗干扰措施。在实验中,此激光汤姆逊散射系统成功地测量出HT-7等离子体的电子温度。     

使用曲面微通道板和感应电荷位置灵敏阳极的软X射线-极紫外光子计数成像探测器研究

本项目对我国空间探测的极紫外(EUV)波段大视场相机所需求的球面光子计数成像探测器的关键技术进行了研究。首先,建立了光阴极材料次级电子产出模型,利用该模型计算了软X射线-EUV波段常用的光电阴极材料—碱卤化物的次级电子产出,分析了微通道板(MCP)的次级电子产出。建立了测量MCP量子探测效率的装置,并推导出MCP量子探测效率的计算公式,测量了MCP在软X射线-EUV波段的量子效率以及MCP量子效率随掠入射角的变化。其次,建立了球面实芯微通道板的制备装置,利用高温热成型方法制备出曲率半径为150 mm球面MCP,利用光刻技术制备出有效直径为48 mm的楔条形感应电荷位置灵敏阳极,在此基础上集成了一套使用球面MCP和感应电荷位置灵敏阳极的两维光子计数成像探测器。再次,研制出包括快速前端模拟电路与后续数字电路的成像读出电路,编制了能矫正图像畸变的图像实时采集和处理软件。最后,建立了MCP探测器空间分辨率、图像线性的检测装置,对研制出的探测器性能进行了检测,检测结果表明:探测器的各项技术指标完全满足要求。     

基于R-C耦合跨阻设计的1 kHz～200 MHz宽带平衡零拍探测器

通过分析平衡零拍探测器的噪声来源，采用电阻-电容（R-C）耦合跨阻电路方案并优化跨阻放大电路结构，实现了一种低噪声、高共模抑制比的宽带平衡零拍探测器，工作带宽为1 kHz～200 MHz。当光功率为8 mW的1550 nm激光入射时：在5 kHz分析频率处散粒噪声功率比电子学噪声功率高12 dB，共模抑制比达到70 dB；在100 MHz分析频率处散粒噪声功率比电子学噪声功率高20 dB，共模抑制比达到66 dB。该探测器可以为低频引力波探测、高速连续变量量子密钥分发和高速量子随机数发生器等应用提供高性能的探测工具。     

非制冷红外探测器读出电路的非均匀性研究

对于长线列的非制冷红外探测器组件, 不同探测元之间的非均匀性是衡量电路设计的关键指标. 为了实现长线列非制冷红外探测器的高性能读出, 本文设计了一种基于电流镜方式的非制冷红外探测器160线列读出电路, 电路由电流镜输入模块、电容负反馈互导放大器模块及相关双采样输出模块组成. 电路采用0.5 μm工艺制作完成. 通过合理设置电路中MOS管的参数和布局电流镜版图, 电路的非均匀性有了明显地改善. 通过测试, 电路的非均匀性小于1%, 器件总功耗约为100 mW, 并具有良好的低噪声特性, 输出噪声小于1 mV, 输出摆幅大于2 V. 该电路与160线列非制冷红外探测器互连后, 能较好地完成红外信号的读出, 在积分时间为20 μups的情况下, 器件的响应为0.294 mV/Ω, 整体性能良好. 该电路的研制对超长线列的非制冷红外冷探测器读出电路研制奠定了重要的技术基础.     

双色热图像信号的电子学处理及图像融合

利用ＢＳＴ非致冷焦平面探测器在２～１４μｍ的光谱响应的特性,可实现双色热成像系统。介绍双色热图的电子学处理及图像融合的部分电路构成及工作原理,电路由信号采焦（０视频信号Ａ／Ｄ化）、图像帧存储、主处理计算机及由可编程逻辑器件的控制与处理电路构成。     

A prototype silicon detector system for space cosmic-ray charge measurement

A readout electronics system used for space cosmic-ray charge measurement for multi-channel silicon detectors is introduced in this paper, including performance measurements. A 64-channel charge sensitive ASIC (VA140) from the IDEAS company is used. With its features of low power consumption, low noise, large dynamic range, and high integration, it can be used in future particle detecting experiments based on silicon detectors.     

用于SCA ASIC测试的数字读出模块设计

高速开关电容阵列(SCA)具有高速采样、低功耗的特点,基于SCA的高速波形数字化是目前高精度时间测量的一个重要研究方向。为此,我们开展SCA芯片的研究,目前已设计完成原型ASIC设计,并正在进行后续版本的改进设计。为便于未来多版本ASIC的测试和评估,需设计具有一定通用性的数字读出模块,本论文工作主要介绍此模块的设计工作以及相应的数据读出软件。数字读出模块基于FPGA实现对待测ASIC的控制、配置及数据读出,采用DDR3片外存储芯片,使用USB3.0等接口进行数据传输;上位机软件基于Python3.7设计,实现了数据采集与波形绘制等功能。目前已使用设计完成的数字读出模块对第2版SCA ASIC进行了初步的测试,测试结果表明,此读出模块工作正常,且SCA芯片输出结果符合预期。     

Interface design in nanosystems of Advanced Superionic Conductors

First attempt of practical realization of new interface engineering approach “from advanced materials to advanced devices” for nanosystems of Advanced Superionic Conductors (ASICs), based on AgI (CuI) compounds is presented. Crystallochemical method of symmetry perfect ASIC//electrode interface searching is developed. Some new theoretical results of ASIC//indifferent electrode conjugated commensurate heteropairs with coherent interfaces and preliminary experimental results of the creation of thin-film supercapacitor — prototype based on the lattice matched heterojunction — are given. Future perspectives of the ASIC//electrode interface design suited for micro(nano)electronics and microsystem technology (MST) are discussed. Paper presented at the Patras Conference on Solid State Ionics — Transport Properties, Patras, Greece, Sept. 14–18, 2004.     

基于SCA ASIC的高精度时间测量原型电子学设计

基于高速波形数字化实现高精度时间测量是核与粒子物理实验读出电子学中的研究热点。本工作针对高精度时间测量的需求基于实验室自主研发的开关电容阵列(Switched Capacitor Array, SCA)专用集成电路(Application Specific Integrated Circuit,ASIC)开展16通道集成的时间测量电子学原型的设计,输入信号经过SCA采样和量化后传输至现场可编程逻辑阵列(Field Programmable Gate Array, FPGA),在FPGA中进行误差修正、时间内插和数字甄别提取出时间信息。目前已在实验室环境下完成此电子学的时间精度测试,测试结果表明,此电子学可以实现好于10 ps RMS(Root Mean Square)的时间精度。     

A prototype scalable readout system for micro-pattern gas detectors

A scalable readout system(SRS) is designed to provide a general solution for different micro-pattern gas detectors in various applications.The system mainly consists of three kinds of modules:the ASIC card,the adapter card and the front-end card(FEC).The ASIC cards,mounted with particular ASIC chips,are designed for receiving detector signals.The adapter card is in charge of digitizing the output signals from several ASIC cards.The PEC,edged-mounted with the adapter,has field-programmable gate array(FPGA)-based reconfigurable logic and I/O interfaces,allowing users to choose different ASIC cards and adapters for different experiments,which expands the system to various applications.The FEC transfers data through Gigabit Ethernet protocol realized by a TCP processor(SiTCP) IP core in FPGA.By assembling a flexible number of FECs in parallel through Gigabit Ethernet,the readout system can be tailored to specific sizes to adapt to the experiment scales and readout requirements.In this paper,two kinds of multi-channel ASIC chip,VA140 and AGET,are applied to verify the scalability of this SRS architecture.Based on this VA140 or AGET SRS,one FEC covers 8 ASIC(VA140) cards handling 512 detector channels,or 4 ASIC(AGET) cards handling 256 detector channels,respectively.More FECs can be assembled in crates to handle thousands of detector channels.     

Design and simulation of a 12-bit, 40 MSPS asynchronous SAR ADC for the readout of PMT signals

High precision and large dynamic range measurement are required in the readout systems for the Water Cherenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO). This paper presents a prototype of a 12-bit 40 MSPS Analog-to-Digital Converter (ADC) Application Specific Integrated Circuit (ASIC) designed for the readout of the LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on a power-efficient Successive Approximation Register (SAR) architecture, which incorporates key parts such as a Capacitive Digital-to-Analog Converter (CDAC), dynamic comparator and asynchronous SAR control logic. The simulation results indicate that the Effective Number Of Bits (ENOB) with a sampling rate of 40 MSPS is better than 10 bits in an input frequency range below 20 MHz, while its core power consumption is 6.6 mW per channel. The above results are good enough for the readout requirements of the WCDA.     

用于像素探测器的高事例率高精度TDC ASIC原型电路的设计与仿真

像素探测器因其优异的位置分辨能力在高能粒子物理实验的内径探测器中有着广泛应用,随着应用场景的发展,许多物理实验要求探测器及其读出电子学也具备高精度时间测量的能力。针对像素探测器时间测量的需求,设计完成了一款具备高事例率处理能力、高精度特点的TDC(Time-to-Digital Conversion) ASIC(Application Specific Integrated Circuit) 原型电路,将来可以作为核心组成部分集成到像素探测器前端读出ASIC中。采用粗细结合的方案完成TDC的设计,其中粗时间测量基于计数器实现,细时间测量采用TAC(Time-to-Amplitude Converter)结合ADC(Time-to-Amplitude Converter)的结构实现,基于130 nm工艺完成了原型电路的设计。对TDC进行仿真,仿真结果表明,该电路可以最多处理连续11个事例,相邻事例的最短时间间隔为500 ps,bin size达到了2 ps,DNL(Differential Non-Linearity)小于2.8 ps,时间测量精度好于5 ps RMS。     

塑料闪烁体阵列探测器读出ASIC中峰值保持电路的设计

塑料闪烁体阵列探测器(PSD,简称塑闪阵列探测器)的输出信号经过前置放大器和滤波成形电路后输出准高斯波形,利用峰值保持电路可对准高斯波形信号的峰值进行采样和保持,以便后续的电子学系统对其进行进一步的分析。本工作采用180 nm CMOS工艺设计并实现了一款峰值保持电路ASIC芯片,每通道主要由跨导放大器(OTA)、电流镜和充电电容三部分电路组成。实验室电子学功能和性能测试结果表明:峰值保持电路功能良好;输入动态范围为33~940 mV,非线性误差优于0.8%,下垂速率好于8.6 μV/μs,峰值探测延迟时间小于35 ns,芯片单通道静态功耗为825 μW,达到设计要求。     

An analogue front-end ASIC prototype designed for PMT signal readout

The Water Cherenkov Detector Array(WCDA) is one of the core detectors in the Large High Altitude Air Shower Observatory(LHAASO),and it consists of 3600 photomultiplier tubes(PMTs).Both high resolution time and charge measurement are required over a large dynamic range from 1 photoelectron(P.E.) to 4000 P.E.The prototype of an analogue front-end Application Specific Integrated Circuit(ASIC) fabricated using Global Foundry 0.35 μm CMOS technology is designed to read out the PMT signal in the WCDA.This ASIC employs leading edge discrimination and an(RC)~4 shaping structure.Combined with the following Time-to-Digital Converter(TDC) and Analog-to-Digital Converter(ADC),both the arrival time and charge of the PMT signal can be measured.Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E.and better than 1% with large input signals(300 P.E.to 4000 P.E.).Besides,this ASIC has a good channel-to-channel isolation of more than 84 dB and the temperature dependency of charge measurement is less than 5% in the range 0-50°C.     

Development of a prototype of the ME readout electronics onboard the HXMT satellite

A prototype of the ME readout electronics onboard the Hard X-ray Modulate Telescope (HXMT) satellite is developed. Application Specific Integrated Chip (ASIC) is used to construct the front end electronics due to a large number of detectors. Field Programmable Gate Array (FPGA) is connected to the ASIC as a state machine controller and data FIFO in the DAQ system. A USB board is designed to communicate between the DAQ system and the computer. The design goals and features, the operation of the system and the preliminary performance of the prototype are described. The testing results show that the design goals of the prototype system have been achieved.