稀土元素掺杂的Hf基栅介质材料研究进展

随着金属氧化物半导体场效应管(MOSFETs)等比缩小到45 nm技术节点,具有高介电常数的栅介质材料(高k材料)取代传统的SiO₂已经成为必然,然而Hf基高k材料在实际应用中仍然存在许多不足,而稀土元素掺杂在提高Hf基栅介质材料的k值、降低缺陷密度、调整MOSFETs器件的阈值电压等方面表现出明显的优势.本文综述了Hf基高k材料的发展历程,面临的挑战,稀土掺杂对Hf基高k材料性能的调节以及未来研究的趋势. 关键词： k栅介质')" href="#">Hf基高k栅介质 稀土掺杂 氧空位缺陷 有效功函数     

Synthesis,characterization and radiation damage studies of high-k dielectric (HfO2) films for MOS device applications

The current trend in miniaturization of metal oxide semiconductor devices needs high-k dielectric materials as gate dielectrics. Among all the high-k dielectric materials, HfO₂ enticed the most attention, and it has already been introduced as a new gate dielectric by the semiconductor industry. High dielectric constant (HfO₂) films (10?nm) were deposited on Si substrates using the e-beam evaporation technique. These samples were characterized by various structural and electrical characterization techniques. Rutherford backscattering spectrometry, X-ray reflectivity, and energy-dispersive X-ray analysis measurements were performed to determine the thickness and stoichiometry of these films. The results obtained from various measurements are found to be consistent with each other. These samples were further characterized by I–V (leakage current) and C–V measurements after depositing suitable metal contacts. A significant decrease in the leakage current and the corresponding increase in device capacitance are observed when these samples were annealed in oxygen atmosphere. Furthermore, we have studied the influence of gamma irradiation on the electrical properties of these films as a function of the irradiation dose. The observed increase in the leakage current accompanied by changes in various other parameters, such as accumulation capacitance, inversion capacitance, flat band voltage, mid-gap voltage, etc., indicates the presence of various types of defects in irradiated samples.     

Ab initio design of high-k dielectrics: La(x)Y1-xAlO3

We use calculations based on density-functional theory in the virtual crystal approximation for the design of high-k dielectrics, which could offer an alternative to silicon dioxide in complementary metal-oxide semiconductor devices. We show that aluminates LaxY1-xAlO3 alloys derived by mixing aluminum oxide with lanthanum and yttrium oxides have unique physical attributes for a possible application as gate dielectrics when stabilized in the rhombohedral perovskite structure, and which are lost in the orthorhombic modification. Stability arguments locate this interesting composition range as 0.2相似文献   

高k介质在新型半导体器件中的应用

当CMOS器件特征尺寸缩小到45 nm以下, SiO₂作为栅介质材料已经无法满足性能和功耗的需要, 用高 k材料替代SiO₂是必然选择. 然而, 由于高 k材料自身存在局限性, 且与器件其他部分的兼容性差, 产生了很多新的问题如界面特性差、 阈值电压增大、 迁移率降低等. 本文简要回顾了高 k栅介质在平面型硅基器件中应用存在的问题以及从材料、 结构和工艺等方面采取的解决措施, 重点介绍了高k材料在新型半导体器件中的应用, 并展望了未来的发展趋势.     

pMOS金属栅极材料的研究进展

随着金属氧化物半导体场效应管(metal-oxide-semiconductor field-effect transistors,MOSFETs)等比缩小迈向45nm技术节点,金属栅极已应用于新型MOSFET器件,改善了与高k栅介质的兼容性,并消除了传统多晶硅栅极的栅耗尽及硼穿透等效应.文章综述了pMOS器件金属栅极材料的发展历程、面临的主要问题以及未来的研究趋势等.     

Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO₂ than SiO₂ in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, I_ON/I_OFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO₂, DIBL shows a reduction of 61.5% over SiO₂. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO₂ when compared to SiO₂. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO₂ based device. From the analysis, it is found that HfO₂ will be a better alternative for the future nanoscale device.     

Elimination of GeO2 and Ge3N4 interfacial transition regions and defects at n-type Ge interfaces: A pathway for formation of n-MOS devices on Ge substrates

The contribution from relatively low-K SiON interfacial transition regions (ITRs) between Si and transition metal (TM) gate dielectrics places a significant limitation on equivalent oxide thickness (EOT) scaling for Si complementary metal-oxide-semiconductor (CMOS) devices. This limitation is equally significant and limiting for Ge CMOS devices. Low-K Ge-based ITRs in Ge devices have also been shown to limit performance and reliability, particular for n-MOS field effect transistors. This article identifies the source of significant electron trapping at interfaces between n-Ge or inverted p-Ge, and Ge oxide, nitride and oxynitride ITRs. This is shown to be an interfacial band alignment issue in which native Ge ITRs have conduction band offset energies smaller than those of TM dielectrics, and trap electrons for negative Ge substrate bias. This article also describes a novel remote plasma processing approach for effectively eliminating any significant native Ge ITRs and using a plasma-processing/annealing process sequence for bonding TM gate dielectrics directly to the Ge substrate surface.     

小尺寸MOSFET隧穿电流解析模型

基于表面势解析模型，通过将多子带等效为单子带，建立了耗尽/反型状态下小尺寸MOSFET直接隧穿栅电流解析模型.模拟结果与自洽解及实验结果均符合较好，表明此模型不仅可用于SiO₂、也可用于高介电常数(k)材料作为栅介质以及叠层栅介质结构MOSFET栅极漏电特性的模拟分析，计算时间较自洽解方法大大缩短，适用于MOS器件电路模拟. 关键词： 隧穿电流 MOSFET 量子机理 解析模型     

Key technologies for dual high-k and dual metal gate integration

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiO_x. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1(NH_4OH:H_2O_2:H_2O = 1 : 1 : 5) and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl_3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl_3/SF_6/O_2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl_3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.     

Gate dielectrics for ultimate CMOS technologies – Limitations and alternative solutions

For nowadays CMOS technologies, the gate oxide thickness has reached a few nanometer range and will be lower than 2 nm for sub-0.1 μ m generations. This scaling of the gate dielectric thickness favors the onset of physical phenomena such as gate polysilicon depletion or quantum effects that limit the MOS device performance in terms of capacitance and leakage current. Moreover, these ultra thin oxide MOS structures are prone to new degradation processes that could reduce their operation lifetime. In this paper, the major limitations raised by the scaling of the gate dielectrics in CMOS technologies are briefly reviewed in terms of MOS capacitance, reliability and new materials issues. More specifically, we first focus on the limitations raised by physical phenomena inherent to MOS capacitors such as polysilicon depletion and quantum effects (carrier confinement and tunneling), impacting their performances. We then address the limitations related to the reliability concerns such as wearout, breakdown, quasi-breakdown, stress-induced leakage current, determining the device lifetime. Finally, the new materials currently envisaged, as replacement solutions in order to overcoming the difficulties due to the gate oxide scaling will be discussed. In particular, the possible solutions based on alternate high permittivity gate dielectrics and metallic gate materials will be emphasized.     

Interface engineering with an MOCVD grown ZnO interface passivation layer for ZrO2-GaAs metal-oxide-semiconductor devices

This work deals with the fabrication of a GaAs metal-oxide-semiconductor device with an unpinned interface environment. An ultrathin (∼2 nm) interface passivation layer (IPL) of ZnO on GaAs was grown by metal organic chemical vapor deposition to control the interface trap densities and to prevent the Fermi level pinning before high-k deposition. X-ray photoelectron spectroscopy and high resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and ZrO₂. By incorporating ZnO IPL, GaAs MOS devices with improved capacitance-voltage and reduced gate leakage current were achieved. The charge trapping behavior of the ZrO₂/ZnO gate stack under constant voltage stressing exhibits an improved interface quality and high dielectric reliability.     

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain(LDD) overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.     

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO₂ layer and are then fully covered by a HfO₂ layer. The HfO₂ is a high-k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance–voltage and conductance–voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.     

Investigation of a 4H-SiC metal-insulation-semiconductor structure with an Al2O3/SiO2 stacked dielectric

Atomic layer deposited(ALD) Al2O3 /dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8°off-axis 4H-SiC(0001) epitaxial wafers are investigated in this paper.The metal-insulation-semiconductor(MIS) capacitors,respectively with different gate dielectric stacks(Al2O3/SiO2,Al2O3,and SiO2) are fabricated and compared with each other.The I-V measurements show that the Al2O3/SiO2 stack has a high breakdown field(≥12 MV/cm) comparable to SiO2,and a relatively low gate leakage current of1×10-7A/cm2 at an electric field of4 MV/cm comparable to Al2O3.The 1-MHz high frequency C-V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage,indicating a less effective charge and slow-trap density near the interface.     

高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响

研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大,肖特基源漏(SBSD) SOI MOSFET的开态电流减小,这表明边缘感应势垒降低效应(FIBL)并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应(FIBS)是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现,源漏与栅是否对准,高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠,高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅,采用高k侧墙并结合堆叠栅结构,可以提高驱动电流.分析结果表明,来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密,从而达到改变势垒高度,调节驱动电流的目的. 关键词： k栅介质')" href="#">高k栅介质 肖特基源漏(SBSD) 边缘感应势垒屏蔽(FIBS) 绝缘衬底上的硅(SOI)     

Organic insulator layer influence on the electrical properties of N,N’-di (2-ethylhexyl) - 3, 4, 9, 10-perylene diimide organic thin-film transistors: Experiment and modeling

In this work, n- type organic thin film transistors (OTFTs) based on different kinds of organic dielectrics were fabricated, characterized and theoretically investigated. Three kinds of organic insulators were applied as dielectric gate which are: divinyl tetramethyl disiloxane-bis (benzo-cyclobutene) (BCB), poly(vinylalcohol) (PVA) and poly (4-vinyl phenol) (PVP). Analytical model was applied to describe the electrical behavior of the fabricated OTFTs and to explain the absence of saturation of the drain current for the device based on PVA dielectric. In addition, Meyer–Neldel rule-grain boundary model was applied for the calculation of total resistance of OTFTs based on different dielectrics materials. The theoretical results of output characteristics and total resistance showed an excellent agreement with the experimental measurements. The experimental and theoretical calculations revealed that the n-channel OTFTs based on BCB as an insulator layer exhibited superior electrical characteristics in terms of threshold voltage, mobility and drain current compared with the devices based on PVA and PVP as a gate insulator layer. The device based on BCB organic insulator layer has the largest mobility of 4?×?10^?3 cm² V^?1 s^?1, the smallest leakage current relative to the devices based on PVA and PVP. While, the device fabricated with PVP organic insulator gate has a large trap density on the PVP-EHPDI interface which causes a pronounced decrease in field effect mobility and consequently drain current.     

Ni全硅化金属栅功函数调节技术研究

通过制备栅内不同掺杂条件的Ni全硅化金属栅电容并分析其C-V和V_fb-EOT特性发现,Ga和Yb较常规的杂质而言具有更好的栅功函数调节能力,能够分别将Ni全硅化金属栅电极功函数调节到价带顶和导带底附近,满足高性能体硅平面互补金属氧化物半导体(CMOS)器件对栅电极功函数的要求. 同时根据电偶极子(Dipole)理论分析了Ga和Yb具有较强栅功函数调节能力的原因. 另外,研究发现栅内掺入Ga或Yb杂质后的Ni全硅化金属栅电容的电容值变大、栅极泄漏电流反而变小,通过对C-V和栅极泄漏电流特性进行分析,对这一现象进行了解释. 关键词： 金属栅电极 功函数 硅化物     

Improved Performance by a Double-Insulator Layer in Organic Thin-Film Transistors

Organic thin film transistors based on pentacene are fabricated by the method of full evaporation. The thickness of insulator film can be controlled accurately, which influences the device operation voltage markedly. Compared to the devices with a single-insulator layer, the electric performance of devices by using a double-insulator as the gate dielectric has good improvement. It is found that the gate leakage current can be reduced over one order of magnitude, and the on-state current can be enhanced over one order of magnitude. The devices with double-insulator layer exhibit field-effect mobility as large as 0.14cm^2/Vs and near the zero threshold voltage. The results demonstrate that using a proper double insulator as the gate dielectrics is an effective method to fabricate OTFTs with high electrical performance.     

Performance analysis of indium phosphide channel based sub-10 nm double gate spin field effect transistor

In this paper, a novel double gate Spin-Field Effect Transistor (DG spin-FET) with indium phosphide (InP) as channel material is evaluated. The proposed spin-FET device is well suited for CMOS technology, as both n and p-type devices can be formed by using parallel and anti-parallel combinations of spin-FET respectively. The proposed device feature size is in sub 10 nm range and therefore is compatible with state of the art integrated circuit technology. The leakage currents have been reduced by employing high-k dielectric (HfO₂). A comparative analysis of the proposed device with the devices reported in the literature confirm that the proposed device has improved on-off ratio and ON current. Besides the device has low transit time and less parasitic capacitances required for high frequency and low power applications respectively.     

Electrical characteristics of Ta2O5 based capacitors with different gate electrodes

Al, W and TiN gate stacks using reactively sputtered thin (15–35 nm) Ta₂O₅ as a high-k dielectric have been investigated. It has been established that the type and the deposition technique of the gate electrode strongly affect the parameters of the structures. RF sputtered tungsten has been established as the most suitable electrode material (giving a nonreactive contact) providing a low leakage current (∼10^-8 A/cm² at 1 MV/cm) through capacitors and a high dielectric constant. The application of Al gate electrodes in the advanced DRAM devices is impeded by the chemical interaction of Al with the Ta₂O₅ films deteriorating the performance of the structures. The radiation-induced defects during the TiN deposition increase the leakage currents for TiN/Ta₂O₅/Si capacitors. A modified Poole–Frenkel conduction mechanism with a tendency for a reduction of the compensation level with increasing Ta₂O₅ thickness was found for W-gate capacitors. Schottky emission at low applied fields and modified Poole–Frenkel mechanism at high fields define the J–V characteristics of Al capacitors. The current through TiN capacitors is governed by ohmic and space charge limited conduction. The post metallization annealing in H₂ reduces the oxide charge but deteriorates both the breakdown fields and the leakage currents for all capacitors studied. The effect is stronger for Al and TiN structures and is accompanied by a reduction of the dielectric constant. PACS 72.80.Sk; 73.40.Qv; 77.55+f; 81.15 Cd