新型缓冲层分区电场调制横向双扩散超结功率器件

为了突破传统横向双扩散金属-氧化物-半导体器件(lateral double-diffused MOSFET)击穿电压与比导通电阻的极限关系,本文在缓冲层横向双扩散超结功率器件(super junction LDMOS-SJ LDMOS)结构基础上,提出了具有缓冲层分区新型SJ-LDMOS结构.新结构利用电场调制效应将分区缓冲层产生的电场峰引入超结(super junction)表面而优化了SJ-LDMOS的表面电场分布,缓解了横向LDMOS器件由于受纵向电场影响使横向电场分布不均匀、横向单位耐压量低的问题.利用仿真分析软件ISE分析表明,优化条件下,当缓冲层分区为3时,提出的缓冲层分区SJ-LDMOS表面电场最优,击穿电压达到饱和时较一般LDMOS结构提高了50%左右,较缓冲层SJ-LDMOS结构提高了32%左右,横向单位耐压量达到18.48 V/μm.击穿电压为382 V的缓冲层分区SJ-LDMOS,比导通电阻为25.6 mΩ·cm2,突破了一般LDMOS击穿电压为254 V时比导通电阻为71.8 mΩ·cm2的极限关系.     

套刻偏差对4H-SiC 浮动结结势垒肖特基二极管的影响研究

4H-SiC浮动结结势垒肖特基二极管与常规结势垒肖特基二极管相比在 相同的导通电阻条件下具有更高的击穿电压. 由p⁺埋层形成的浮动结与主结p⁺区 之间的套刻对准是实现该结构的一项关键技术. 二维模拟软件ISE的模拟结果表明, 套刻偏差的存在会明显影响器件的击穿特性, 随着偏差的增大击穿电压减小. 尽管主结和埋层的交错结构与对准结构具有相似的击穿特性, 但是当正向电压大于2 V后, 交错结构的串联电阻更大.     

GaN基肖特基势垒二极管结构优化研究进展

作为宽禁带半导体器件,GaN基肖特基势垒二极管(SBD)有耐高压、耐高温、导通电阻小等优良特性,这使得它在电力电子等领域有广泛应用。本文首先综述了SBD发展要解决的问题;然后,介绍了GaN SBD结构、工作原理及结构优化研究进展;接下来,总结了AlGaN/GaN SBD结构、工作原理及结构优化研究进展,并着重从AlGaN/GaN SBD的外延片结构、肖特基电极结构以及边缘终端结构等角度,阐述了这些结构的优化对AlGaN/GaN SBD性能的影响;最后,对器件进一步的发展方向进行了展望。     

高k介质电导增强SOI LDMOS机理与优化设计

本文提出一种高k介质电导增强SOI LDMOS新结构（HK CE SOI LDMOS）,并研究其机理. HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻. 借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系. 结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%–18%,同时比导通电阻降低13%–20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题. 关键词： k介质')" href="#">高k介质 绝缘体上硅 (SOI) 击穿电压 比导通电阻     

复合漏电模型建立及阶梯场板GaN肖特基势垒二极管设计

准垂直GaN肖特基势垒二极管(SBD)因其低成本和高电流传输能力而备受关注.但其主要问题在于无法很好地估计器件的反向特性,从而影响二极管的设计.本文考虑了GaN材料的缺陷以及多种漏电机制,建立了复合漏电模型,对准垂直Ga N SBD的特性进行了模拟,仿真结果与实验结果吻合.基于此所提模型设计出具有高击穿电压的阶梯型场板结构准垂直GaN SBD.根据漏电流、温度和电场在反向电压下的相关性,分析了漏电机制和器件耐压特性,设计的阶梯型场板结构准垂直GaN SBD的Baliga优值BFOM达到73.81 MW/cm~2.     

具有p-GaN岛状埋层耐压结构的横向AlGaN/GaN高电子迁移率晶体管

GaN基高电子迁移率晶体管(HEMT)相对较低的击穿电压严重限制了其大功率应用.为了进一步改善器件的击穿特性,通过在n-GaN外延缓冲层中引入六个等间距p-GaN岛掩埋缓冲层(PIBL)构成p-n结,提出一种基于p-GaN埋层结构的新型高耐压AlGaN/GaN HEMT器件结构.Sentaurus TCAD仿真结果表明,在关态高漏极电压状态下,p-GaN埋层引入的多个反向p-n结不仅能够有效调制PIBL AlGaN/GaN HEMT的表面电场和体电场分布,而且对于缓冲层泄漏电流有一定的抑制作用,这保证了栅漏间距为10μm的PIBL HEMT能够达到超过1700 V的高击穿电压(BV),是常规结构AlGaN/GaN HEMT击穿电压(580 V)的3倍.同时,PIBL结构AlGaN/GaN HEMT的特征导通电阻仅为1.47 m?·cm~2,因此获得了高达1966 MW·cm~(-2)的品质因数(FOM=BV~2/R_(on,sp)).相比于常规的AlGaN/GaN HEMT,基于新型p-GaN埋岛结构的HEMT器件在保持较低特征导通电阻的同时具有更高的击穿电压,这使得该结构在高功率电力电子器件领域具有很好的应用前景.     

具有N型缓冲层REBULF Super Junction LDMOS

针对功率集成电路对低损耗LDMOS (lateral double-diffused MOSFET)类器件的要求,在N型缓冲层super junction LDMOS (buffered SJ-LDMOS)结构基础上, 提出了一种具有N型缓冲层的REBULF (reduced BULk field) super junction LDMOS结构. 这种结构不但消除了N沟道SJ-LDMOS由于P型衬底带来的衬底辅助耗尽效应问题, 使super junction的N区和P区电荷完全补偿, 而且同时利用REBULF的部分N型缓冲层电场调制效应, 在表面电场分布中引入新的电场峰而使横向表面电场分布均匀, 提高了器件的击穿电压. 通过优化部分N型埋层的位置和参数, 利用仿真软件ISE分析表明, 新型REBULF SJ-LDMOS 的击穿电压较一般LDMOS提高了49%左右, 较文献提出的buffered SJ-LDMOS结构提高了30%左右. 关键词： lateral double-diffused MOSFET super junction 击穿电压 表面电场     

电荷失配对SiC半超结垂直双扩散金属氧化物半导体场效应管击穿电压的影响

Si C半超结垂直双扩散金属氧化物半导体场效应管(VDMOSFET)相对于常规VDMOSFET在相同导通电阻下具有更大击穿电压.在N型外延层上进行离子注入形成半超结结构中的P柱是制造Si C半超结VDMOSFET的关键工艺.本文通过二维数值仿真研究了离子注入导致的电荷失配对4H-Si C超结和半超结VDMOSFET击穿电压的影响,在电荷失配程度为30%时出现半超结VDMOSFET的最大击穿电压.在本文的器件参数下,P柱浓度偏差导致击穿电压降低15%时,半超结VDMOSFET柱区浓度偏差范围相对于超结VDMOSFET可提高69.5%,这意味着半超结VDMOSFET对柱区离子注入的控制要求更低,工艺制造难度更低.     

半超结SiGe高压快速软恢复开关二极管

将SiGe材料的优异性能与半超结结构的优势相结合,提出了一种半超结SiGe功率二极管, 可适应高频化电力电子电路对功率二极管低通态压降、高击穿电压、较小的反向漏电流以及快而软的反向恢复特性的要求,显著提高器件的各种特性. 关键词： 半超结 硅锗二极管 高压 快速软恢复     

漂移区表面阶梯掺杂LDMOS的击穿电压模型

提出表面阶梯掺杂(SD：Step Doping on surface)LDMOS的二维击穿电压模型.基于求解多区二维Poisson方程,获得SD结构表面电场的解析式.借助此模型,研究其结构参数对击穿电压的影响;计算优化漂移区浓度和厚度与结构参数的关系,给出获得最大击穿电压的途径.数值结果,解析结果和试验结果符合较好.漂移区各区和衬底电场相互调制,在漂移区中部产生新的峰值,改善电场分布;高掺杂区位于表面,降低了正向导通电阻.结果表明：SD结构较常规结构击穿电压从192V提高到242V,导通电阻下降33%. 关键词： 阶梯掺杂 模型 优化 调制     

Analysis and simulation of a 4H-SiC semi-superjunction Schottky barrier diode for softer reverse-recovery

In this paper, a 4H-SiC semi-superjunction (SJ) Schottky barrier diode is analysed and simulated. The semi-SJ structure has an optimized design and a specific on-resistance lower than that of conventional SJ structures, which can be achieved without increasing the process difficulty. The simulation results show that the specific on-resistance and the softness factor depend on the aspect and thickness ratios, and that by using the semi-SJ structure, specific on-resistance can be reduced without decreasing the softness factor. It is observed that a trade-off exists between the specific on-resistance and the softness of the diode.     

An oxide filled extended trench gate super junction MOSFET structure

This paper proposes an oxide filled extended trench gate super junction (SJ) MOSFET structure to meet the need of higher frequency power switches application. Compared with the conventional trench gate SJ MOSFET, new structure has the smaller input and output capacitances, and the remarkable improvements in the breakdown voltage, on-resistance and switching speed. Furthermore, the SJ in the new structure can be realized by the existing trench etching and shallow angle implantation, which offers more freedom to SJ MOSFET device design and fabrication.     

Improvement on short-circuit ability of SiC super-junction MOSFET with partially widened pillar structure

A novel 1200 V SiC super-junction (SJ) MOSFET with a partially widened pillar structure is proposed and investigated by using the two-dimensional numerical simulation tool. Based on the SiC SJ MOSFET structure, a partially widened P-region is added at the SJ pillar region to improve the short-circuit (SC) ability. After investigating the position and doping concentration of the widened P-region, an optimal structure is determined. From the simulation results, the SC withstand times (SCWTs) of the conventional trench MOSFET (CT-MOSFET), the SJ MOSFET, and the proposed structure at 800 V DC bus voltage are 15 μs, 17 μs, and 24 μs, respectively. The SCWTs of the proposed structure are increased by 60% and 41.2% in comparison with that of the other two structures. The main reason for the proposed structure with an enhanced SC capability is related to the effective suppression of saturation current at the high DC bias conditions by using a modulated P-pillar region. Meanwhile, a good Baliga's FOM ($BV^{2}/R_{\rm on}$) also can be achieved in the proposed structure due to the advantage of the SJ structure. In addition, the fabrication technology of the proposed structure is compatible with the standard epitaxy growth method used in the SJ MOSFET. As a result, the SJ structure with this feasible optimization skill presents an effect on improving the SC reliability of the SiC SJ MOSFET without the degeneration of the Baliga's FOM.     

A super junction SiGe low-loss fast switching power diode

This paper proposes a novel super junction (SJ) SiGe switching power diode which has a columnar structure of alternating p^- and n^- doped pillar substituting conventional n^- base region and has far thinner strained SiGe p⁺ layer to overcome the drawbacks of existing Si switching power diode. The SJ SiGe diode can achieve low specific on-resistance, high breakdown voltages and fast switching speed. The results indicate that the forward voltage drop of SJ SiGe diode is much lower than that of conventional Si power diode when the operating current densities do not exceed 1000 A/cm², which is very good for getting lower operating loss. The forward voltage drop of the Si diode is 0.66V whereas that of the SJ SiGe diode is only 0.52 V at operating current density of 10 A/cm². The breakdown voltages are 203 V for the former and 235 V for the latter. Compared with the conventional Si power diode, the reverse recovery time of SJ SiGe diode with 20 per cent Ge content is shortened by above a half and the peak reverse current is reduced by over 15%. The SJ SiGe diode can remarkably improve the characteristics of power diode by combining the merits of both SJ structure and SiGe material.     

Improvement of reverse blocking performance in vertical power MOSFETs with Schottky–drain-connected semisuperjunctions

To enhance the reverse blocking capability with low specific on-resistance,a novel vertical metal-oxidesemiconductor field-effect transistor(MOSFET) with a Schottky-drian(SD) and SD-connected semisuperjunctions(SDD-semi-SJ),named as SD-D-semi-SJ MOSFET is proposed and demonstrated by two-dimensional(2D) numerical simulations.The SD contacted with the n-pillar exhibits the Schottky-contact property,and that with the p-pillar the Ohmic-contact property.Based on these features,the SD-D-semi-SJ MOSFET could obviously overcome the great obstacle of the ineffectivity of the conventional superjunctions(SJ) or semisuperjunctions(semi-SJ) for the reverse applications and achieve a satisfactory trade-off between the reverse breakdown voltage(BV) and the specific on-resistance(R_(on)A).For a given pillar width and n-drift thickness,there exists a proper range of n-drift concentration(N),in which the SD-D-semi-SJ MOSFET could exhibit a better trade-off of R_(on)A-BV compared to the predication of SJ MOSFET in the forward applications.And what is much valuable,in this proper range of N,the desired BV and good trade-off could be achieved only by determining the pillar thickness,with the top assist layer thickness unchanged.Detailed analyses have been carried out to get physical insights into the intrinsic mechanism of R_(on)A-BV improvement in SD-D-semi-SJ MOSFET.These results demonstrate a great potential of SD-D-semi-SJ MOSFET in reverse applications.     

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET) structure with side-wall p-type pillar (p-pillar) and wrap n-type pillar (n-pillar) in the n-drain was investigated by utilizing Silvaco TCAD simulations. The optimized structure mainly includes a p$+$ buried region, a light n-type current spreading layer (CSL), a p-type pillar region, and a wrapping n-type pillar region at the right and bottom of the p-pillar. The improved structure is named as SNPPT-MOS. The side-wall p-pillar region could better relieve the high electric field around the p$+$ shielding region and the gate oxide in the off-state mode. The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance ($R_{\rm on,sp}$). As a result, the SNPPT-MOS structure exhibits that the figure of merit (FoM) related to the breakdown voltage ($V_{\rm BR}$) and $R_{\rm on,sp}$ ($V_{\rm BR}^{2}R_{\rm on,sp}$) of the SNPPT-MOS is improved by 44.5%, in comparison to that of the conventional trench gate SJ MOSFET (full-SJ-MOS). In addition, the SNPPT-MOS structure achieves a much faster-witching speed than the full-SJ-MOS, and the result indicates an appreciable reduction in the switching energy loss.     

具有L型源极场板的双槽绝缘体上硅高压器件新结构

为了提高小尺寸绝缘体上硅(SOI)器件的击穿电压,同时降低器件比导通电阻,提出了一种具有L型源极场板的双槽SOI高压器件新结构.该结构具有如下特征:首先,采用了槽栅结构,使电流纵向传导面积加宽,降低了器件的比导通电阻;其次,在漂移区引入了Si O2槽型介质层,该介质层的高电场使器件的击穿电压显著提高;第三,在槽型介质层中引入了L型源极场板,该场板调制了漂移区电场,使优化漂移区掺杂浓度大幅增加,降低了器件的比导通电阻.二维数值仿真结果表明:与传统SOI结构相比,在相同器件尺寸时,新结构的击穿电压提高了151%,比导通电阻降低了20%;在相同击穿电压时,比导通电阻降低了80%.与相同器件尺寸的双槽SOI结构相比,新结构保持了双槽SOI结构的高击穿电压特性,同时,比导通电阻降低了26%.     

Ultra-low specific on-resistance vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench(HK TG VDMOS) is proposed in this paper.The HK TG VDMOS features a high-k(HK) trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage(BV).Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction(SJ) vertical double-diffused metal-oxide semiconductor(VDMOS),the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS(TG VDMOS) and conventional superjunction trench gate VDMOS(SJ TG CDMOS).     

具有P型覆盖层新型超级结横向双扩散功率器件

为了设计功率集成电路所需要的低功耗横向双扩散金属氧化物半导体器件(lateral double-diffused MOSFET), 在已有的N型缓冲层超级结LDMOS(N-buffered-SJ-LDMOS)结构基础上, 提出了一种具有P型覆盖层新型超级结LDMOS结构(P-covered-SJ-LDMOS). 这种结构不但能够消除传统的N沟道SJ-LDMOS由于P型衬底产生的衬底辅助耗尽问题, 使得超级结层的N区和P区的电荷完全补偿, 而且还能利用覆盖层的电荷补偿作用, 提高N型缓冲层浓度, 从而降低了器件的比导通电阻. 利用三维仿真软件ISE分析表明, 在漂移区长度均为10 μm的情况下, P-covered-SJ-LDMOS的比导通电阻较一般SJ-LDMOS结构降低了59%左右, 较文献提出的N型缓冲层 SJ-LDMOS(N-buffered-SJ-LDMOS)结构降低了43%左右.     

Study of a double epi-layers SiC junction barrier Schottky rectifiers embedded P layer in the drift region

<正>This paper proposes a double epi-layers 4H—SiC junction barrier Schottky rectifier(JBSR) with embedded P layer (EPL) in the drift region.The structure is characterized by the P-type layer formed in the n-type drift layer by epitaxial overgrowth process.The electric field and potential distribution are changed due to the buried P-layer,resulting in a high breakdown voltage(BV) and low specific on-resistance(R_(on,sp)).The influences of device parameters,such as the depth of the embedded P+ regions,the space between them and the doping concentration of the drift region,etc.,on BV and R_(on,sp) are investigated by simulations,which provides a particularly useful guideline for the optimal design of the device.The results indicate that BV is increased by 48.5%and Baliga's figure of merit(BFOM) is increased by 67.9%compared to a conventional 4H-SiC JBSR.