Performance improvement of charge trap flash memory by using a composition-modulated high-k trapping layer

A composition-modulated （HfO2）x（Al2O3）1-x charge trapping layer is proposed for charge trap flash memory by controlling the A1 atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated （HfO2）x（Al2O3）l-x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application.     

Charge storage characteristics in Al/AlN/Si metal–insulator–semiconductor structure based on deep traps in AlN layer

Charge storage characteristics in an Al/AlN/p-Si metal–insulator–semiconductor (MIS) structure have been investigated by capacitance–voltage and long-term capacitance measurements. Good program/erase behavior is observed in the AlN/Si structure, which is attributed to the trapping and detrapping of charges in deep traps of the AlN layer. In the long-term retention mode, a clear memory window is found 2000 s after removing a program/erase voltage of ±3 V, indicating good charge retention capability of the MIS structure. Further investigation shows that for a program pulse width of 500 ms, the charge storage does not occur when the pulse amplitude is smaller than a threshold value of ∼1 V. The trapped charge density increases linearly with increase of the pulse amplitude (>1 V) and tends to saturate at 2.5 V. With increasing program pulse width, the trapped charged density increases a little more than logarithmically. PACS 73.40.Kp; 72.20.Jv; 71.55.Eq     

电荷俘获存储器数据保持特性第一性原理研究

本文研究HfO₂掺入Al替位Hf杂质和氧空位共同掺杂对电荷俘获型存储器存储特性的影响. HfO₂作为高介电常数材料由于具有缩小器件尺寸、提高器件性能等优势, 被广泛用于CTM的俘获层. 采用MS和VASP研究了HfO₂俘获层中掺入Al对氧空位形成能的影响. 同时计算了两种缺陷在不同距离下的相互作用能. 计算结果表明在HfO₂中掺入Al使得氧空位的形成能降低, 并且三配位氧空位的形成能比四配位氧空位的形成能降低的更多. 通过研究Al和三配位氧空位两种缺陷间不同距离的三种情况, 计算结果表明当缺陷间距为2.107 Å时, 体系的电荷俘获能最大; 量子态数最多; 布居数最小、Al–O键最长. 通过研究三种体系写入空穴后键长的变化, 得出当缺陷间距为2.107 Å时, 写入空穴后体系的Al–O键长变化最小. 以上研究结果表明, 掺入Al后可以有效提高电荷俘获型存储器的数据保持能力. 因而本文的研究为改善电荷俘获型存储器数据保持特性提供一定的理论指导.     

Low voltage program-erasable Pd-Al_2O_3-Si capacitors with Ru nanocrystals for nonvolatile memory application

Pd-Al2O3-Si capacitors with Ru nanocrystals are fabricated and electrically characterized for nonvolatile memory application.While keeping the entire insulator Al2O3thickness fixed,the memory window has a strong dependence on the tunneling layer thickness under low operating voltages,whereas it has weak dependence under high operating voltages.As for the optimal configuration comprised of 6-nm tunneling layer and 22-nm blocking layer,the resulting memory window increases from 1.5 V to 5.3 V with bias pulse increasing from 10 5s to 10 2s under±7 V.A ten-year memory window as large as 5.2 V is extrapolated at room temperature after±8 V/1 ms programming/erasing pulses.     

LaON/SiO2和HfON/SiO2双隧穿层MONOS存储器存储特性的比较

本文对比研究了LaON/SiO₂和HfON/SiO₂双隧穿层MONOS存储器的存储特性. 实验结果表明,LaON/SiO₂双隧穿层MONOS存储器具有较大的存储窗口,快的编程/擦除速度及好的疲劳和保持特性. 其机理在于LaON较大的介电常数有效提高了编程/擦除过程中载流子的注入效率,较小的O 扩散系数减少了界面陷阱,从而减少了保持期间存储电荷通过陷阱辅助隧穿的泄漏. 而且N的结合在界面附近形成了强的La-N,Hf-N 和O-N键,可有效降低编程/擦除循环应力对界面的损伤,使器件具有好的疲劳特性. 此外,研究了退火温度对存储特性的影响,结果表明800 ℃退火样品的存储特性比700 ℃退火的好,这是因为800 ℃时NO退火可在LaON（HfON）中引入更多的N,且能更好释放应力,使介质中缺陷减少. 关键词： MONOS 双隧穿层 LaON HfON     

电荷俘获存储器的过擦现象

基于密度泛函理论的第一性原理平面波超软赝势方法和VASP软件对电荷俘获存储器过擦现象进行了分析研究.通过形成能的计算,确定了含有氮空位缺陷的Si3N4和含有间隙氧缺陷的Hf O2作为研究的对象;俘获能的计算结果表明两种体系对电子的俘获能力比对空穴的大,因而对两体系擦写载流子确定为电子.分别计算了Hf O2和Si3N4擦写前后的能量、擦写前后电荷分布变化、吸附能和态密度,以说明过擦的微观机理.对能量和擦写电荷变化的研究,表明Si3N4相比于Hf O2,其可靠性较差,且Si3N4作为俘获层,在一个擦写周期后,晶胞中电子出现减少现象;界面吸附能的研究表明,Si3N4相比于Hf O2在缺陷处更容易与氧进行电子交换;最后,通过对态密度的分析表明Si3N4和Hf O2在对应的缺陷中均有缺陷能级俘获电子,前者为浅能级俘获,后者为深能级俘获.综上分析表明,Si3N4在氮空位的作用下,缺陷附近原子对电子的局域作用变弱,使得Si3N4作为俘获层时,材料本身的电子被擦出,使得擦操作时的平带偏移电压增大,导致存储器发生过擦.本文的研究结果揭示了过擦的本质,对提高电荷俘获存储器的可靠性以及存储特性有着重要的指导意义.     

Memory Effect of Metal--Insulator--Silicon Capacitors with SiO2/HfO2/Al2O3 Dielectrics

Charge trapping characteristics of the metal-insulator-silicon （MIS） capacitors with Si02/HfO2//A12O3 stacked dielectrics are investigated for memory applications＇. A capacitance-voltage hysteresis memory window as large as 7.3 V is achieved for the gate voltage sweeping of ±12 V, and a fiat-band voltage shift of 1.5 V is observed in terms of programming under 5 V and I ms. Furthermore, the time- and voltage-dependent charge trapping characteristics are also demonstrated, the former is related to charge trapping saturation and the latter is ascribed to variable tunnelling barriers for electron injecting and discharging under different voltages.     

Electrical and material characterization of tantalum pentoxide (Ta2O5) charge trapping layer memory

In this experiment, tantalum pentoxide (Ta₂O₅) was used in a metal/oxide/high-k Ta₂O₅/oxide/silicon (MOHOS) novel nanocrystal memory as a trapping layer. Post-annealing treatment, which can passivate defects and improve the material quality of the high-k dielectric, was applied to optimize device performance for a better memory window and faster P/E (program/erase) cycle. Material and electrical characterization techniques including X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), and electrical measurements were performed to analyze the device under different annealing conditions. The Ta₂O₅ charge trapping layer memory annealed at 900 °C had a higher window of 3.3 V in the current-voltage (C-V) hysteresis loop, and a higher charge retention capability than the samples prepared under various annealing conditions. These higher levels were due to the higher probability of deep-level charge trapping and lower leakage current.     

Al掺杂对HfO2俘获层可靠性影响第一性原理研究

采用基于MS(Materials Studio)软件和密度泛函理论的第一性原理方法, 研究了HfO₂ 俘获层的电荷俘获式存储器(Charge Trapping Memory, CTM)中电荷的保持特性以及耐擦写性. 在对单斜晶HfO₂中四配位氧空位(V_O4) 缺陷和V_O4 与Al替位Hf掺杂的共存缺陷体(Al+V_O4)两种超晶胞模型进行优化之后, 分别计算了其相互作用能、形成能、Bader电荷、态密度以及缺陷俘获能. 相互作用能和形成能的计算结果表明共存缺陷体中当两种缺陷之间的距离为2.216 Å时, 结构最稳定、缺陷最容易形成; 俘获能计算结果表明, 共存缺陷体为双性俘获, 且与V_O4缺陷相比, 俘获能显著增大; Bader电荷分析表明共存缺陷体更有利于电荷保持; 态密度的结果说明共存缺陷体对空穴的局域能影响较强; 计算两种模型擦写电子前后的能量变化表明共存缺陷体的耐擦写性明显得到了改善. 因此在HfO₂俘获层中可以通过加入Al杂质来改善存储器的保持特性和耐擦写性. 本文的研究可为改善CTM数据保持特性和耐擦写性提供一定的理论指导.     

退火工艺对LaTiON和HfLaON存储层金属-氧化物-氮化物-氧化物-硅存储器特性的影响

采用反应溅射法, 分别制备以LaTiON, HfLaON为存储层的 金属-氧化物-氮化物-氧化物-硅 电容存储器, 研究了淀积后退火气氛(N₂, NH₃)对其存储性能的影响. 分析测试表明, 退火前LaTiON样品比HfLaON 样品具有更好的电荷保持特性, 但后者具有更大的存储窗口 (编程/擦除电压为+/-12 V时4.8 V); 对于退火样品, 由于NH₃的氮化作用, NH₃退火样品比N₂退火样品表现出更快的编程/擦除速度、更好的电荷保持特性和疲劳特性. 当编程/擦除电压为+/-12 V时, NH₃退火HfLaON样品的存储窗口为3.8 V, 且比NH₃退火LaTiON样品具有更好的电荷保持特性和疲劳特性.     

负电荷层对a-IGZO TFT阈值电压的影响

采用脉冲直流磁控溅射的方式沉积In-Ga-Zn-O (IGZO)膜层作为TFT的有源层.在TFT沟道处的有源层和绝缘层的界面上, 通过溅射法制作一定厚度的负电荷层对阈值电压(V_th)进行调制, 使得V_th由-3.8 V升高至-0.3 V, 器件由耗尽型向增强型转变.通过增加Al₂O₃作为负电荷层, 可有效地将V_th控制在0 V附近, 并且提高其器件稳定性, 得到较好的电学特性:电流开关比I_on/I_off>10⁹, 亚阈值摆幅SS为0.2 V/dec, 阈值电压V_th为-0.3 V, 迁移率μ为9.2 cm² /(V·s).     

Improved characteristics for MOHOS memory with oxygen-rich GdO as charge storage layer annealed by NH3

Characteristics of metal–oxide–high-k–oxide–silicon (MOHOS) memories with oxygen-rich or oxygen-deficient GdO as charge storage layer annealed by NH₃ or N₂ are investigated. Transmission electron microscopy, X-ray photoelectron spectroscopy and X-ray diffraction are used to analyze the cross-sectional quality, composition and crystallinity, respectively, of the stacked gate dielectric with a structure of Al/Al₂O₃/GdO/SiO₂/Si. The MOHOS capacitor with oxygen-rich GdO annealed in NH₃ exhibits a good trade-off among its memory properties: large memory window (4.8 V at ±12 V, 1 s), high programming speed (2.6 V at ±12 V/100 μs), good endurance and retention properties (window degradation of 5 % after 10⁵ program/erase cycles and charge loss of 18.6 % at 85 °C after 10 years, respectively) due to passivation of oxygen vacancies, generation of deep-level traps in the grain boundaries of the GdO layer and suppression of the interlayer between GdO and SiO₂ by the NH₃ annealing.     

Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed.The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing(P/E) operations at various P/E voltages are discussed.The simulated results show that present memory exhibits a large memory window of 57.5 V,and a high read current on/off ratio of ≈ 10~3.Compared with the reported experimental results,these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects,which shows great promise in device designing and practical application.     

不同Sb含量p-SnO2薄膜的制备和特性

采用化学气相沉积方法, 利用Sb₂O₃/SnO作为源材料, 在蓝宝石衬底上制备出不同Sb掺杂量的SnO₂薄膜, 并在此基础上制作出p-SnO₂:Sb/n-SnO₂同质p-n 结器件. 研究表明, 随着Sb含量的增加, 样品表面变得平滑, 晶粒尺寸逐渐增大, 且晶体质量有所改善, 发现少量Sb的掺入可以起到表面活化剂的作用. Hall测量结果证实适量Sb的掺杂可以使SnO₂呈现p型导电特性, 当Sb₂O₃/SnO的质量比为1:5时, 其电学参数为最佳值. 此外, p-SnO₂:Sb/n-SnO₂同质p-n结器件展现出良好的整流特性, 其正向开启电压为3.4 V.     

改善Si3N4俘获层过擦现象的第一性原理研究

采用第一性原理方法对如何改善电荷俘获存储器的过擦现象进行了研究. 过擦是由于氮空位中Si原子对电荷的局域能力弱导致, 因此, 在Si₃N₄超胞中分别建立了以C, N, O替换氮空位中的Si原子的缺陷结构作为本文的研究模型. 分别计算了擦写之后体系的巴德电荷分布、相互作用能、态密度, 借以分析替位原子对过擦的影响. 巴德电荷分布的计算结果表明, Si₃N₄在O替位128号Si后的过擦现象被明显改善; C替位128号Si也可以改善过擦, 但由于C替位对电荷的局域作用变弱, 不利于电荷的存储实现; N替位128号Si则不能改善过擦; 而在162和196号Si位置, 三种原子的替换均无法改善过擦现象. 相互作用能的研究表明, 在128号Si位置, 三种原子都能够和氮空位形成团簇, 在体系中稳定存在. 特别地, O替位Si后, 体系中两缺陷的相互吸引作用最弱, 从而写入的电荷能够短暂的打破O团簇的稳定性, 实现电荷重构, 将电荷局域在O团簇周围. 此外, 态密度的分析结果表明O在128号Si位置能够在Si₃N₄禁带中引入深能级缺陷, 深能级局域电荷的能力强. 以上分析证明, O替位可以很好的改善Si₃N₄中的过擦现象. 本文的研究结果为电荷俘获存储器改善过擦提供了一种方法, 对提高器件的电荷保持特性和优化存储窗口具有指导意义.     

Effects of charge storage dielectric thickness on hybrid gadolinium oxide nanocrystal and charge trapping nonvolatile memory

The characteristics of hybrid gadolinium oxide nanocrystal (Gd₂O₃-NC) and gadolinium oxide charge trapping (Gd₂O₃-CT) memories were investigated with different Gd₂O₃ film thickness. By performing the rapid thermal annealing on Gd₂O₃ films with different thickness, the Gd₂O₃-NCs with the diameter of 6–9 nm for charge storage, surrounded by the amorphous Gd₂O₃ (α-Gd₂O₃) layer, were formed. The α-Gd₂O₃ layer was considered to be the charge trapping layer, resulting in the large memory window of Gd₂O₃-NC/CT memories with thick Gd₂O₃ film. The charge trapping energy level of the Gd₂O₃-NCs and α-Gd₂O₃ layer was extracted to be 0.16 and 0.45 eV respectively by using the temperature-dependent retention measurement. Further, after a 10⁶ program/erase cycling operation, the memory with thin Gd₂O₃ film can be predicted to sustain a 94% memory window of the first cycling one while the memory with thick Gd₂O₃ film suffered from a 30% charge loss because of the traps within the α-Gd₂O₃ layer. The Gd₂O₃ film thickness of 10 nm was optimized to exhibit superior performances of the Gd₂O₃-NC/CT memory, which can be applied into the nonvolatile memory.     

Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

In this work, the trap-assisted tunneling(TAT) mechanism is modeled as a two-step physical process for charge trapping memory(CTM). The influence of the TAT mechanism on CTM performance is investigated in consideration of various trap positions and energy levels. For the simulated CTM structure, simulation results indicate that the positions of oxide traps related to the maximum TAT current contribution shift towards the substrate interface and charge storage layer interface during time evolutions in programming and retention operations, respectively. Lower programming voltage and retention operations under higher temperature are found to be more sensitive to tunneling oxide degradation.     

多层栅介质层有机薄膜晶体管的存储与光响应特性

在真空室内一次性制备了具有多层栅介质层结构的有机薄膜晶体管(OTFTs).结果表明,制备的OTFTs具有电控开关、存储和光敏多重功能特性.分析认为,存储特性归功于器件的结构,采用了分离的CaF2纳米粒子岛作为电荷俘获中心.在光照环境下,观察到了两种不同类型的光响应特性.快速的光响应来自于有源层吸收了能量大于带隙的光子所...     

High performance uncooled InAsSbP/InGaAs photodiodes for the 1.8–3.4 μm wavelength range

Room temperature In_0.97Ga_0.03As photodiodes with an InAs_0.36Sb_0.20P_0.44 transparent window layer operating in the mid-infrared region over the wavelength range 1.8–3.4 μm are reported. The InAs_0.36Sb_0.20P_0.44/In_0.97Ga_0.03As heterojunction photodiodes were grown on p-type (100) InAs substrates by liquid phase epitaxy (LPE). Basic detector characteristics have been measured and compared with other detectors in this wavelength range. The typical detectivity of the photodiodes is 1.2 × 10¹⁰ cm Hz^1/2/W at room temperature, which compares very favourably with that of TE cooled HgCdTe and is at least three times that of cooled PbSe photoconductors. The InAs_0.36Sb_0.20P_0.44/In_0.97Ga_0.03As heterojunction photodiodes offer the advantage of increased sensitivity and extended wavelength response at room temperature compared with that of currently available commercial photodetectors, making them an attractive alternative for a number of mid-infrared applications including optical gas sensors and infrared spectrometers.     

(Cu,N)共掺杂TiO2/MoS2异质结的电子和光学性能:杂化泛函HSE06

在密度泛函理论的基础上,系统地研究了Cu/N（共）掺杂的TiO₂/MoS₂异质结体系的几何结构、电子结构和光学性质.计算发现,TiO₂/MoS₂异质结的带隙相比于纯的TiO₂（101）表面明显变小,Cu/N（共）掺杂TiO₂/MoS₂异质结体系的禁带宽度也明显地减小,这导致光子激发能量的降低和光吸收能力的提高.通过计算Cu/N（共）掺杂TiO₂/MoS₂的差分电荷密度,发现光生电子与空穴积累在掺杂后的TiO₂（101）表面和单层MoS₂之间,这表明掺杂杂质体系可以有效地抑制光生电子-空穴对的复合.此外,我们计算了在不同压力下TiO₂/MoS₂异质结的几何、电子和光学性质,发现适当增加压力可以有效提高异质结的光吸收性能.本文结果表明,Cu/N（共）掺杂TiO₂/MoS₂异质结和对TiO₂/MoS₂异质结加压都能有效地提高材料的光学性能.