Degradation of Ultra-Thin Gate Oxide NMOSFETs under CVDT and SHE Stresses

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT)stresses are studied using NMOSFET with 1.4- nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown.     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

Actions of negative bias temperature instability (NBTI) and hot carriers in ultra-deep submicron p-channel metal——oxide——semiconductor field-effect transistors (PMOSFETs)

Hot carrier injection (HCI) at high temperatures and different values of gate bias V_g has been performed in order to study the actions of negative bias temperature instability (NBTI) and hot carriers. Hot-carrier-stress-induced damage at V_g=V_d, where V_d is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different: the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal--oxide--semiconductor field-effect transistors (PMOSFETs). We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.     

应力导致的薄栅氧化层漏电流瞬态特性研究

分别研究了FN隧穿应力和热空穴(HH)应力导致的薄栅氧化层漏电流瞬态特性.在这两种应力条件下,应力导致的漏电流(SILC)与时间的关系均服从幂函数关系,但是二者的幂指数不同.热空穴应力导致的漏电流中,幂指数明显偏离-1,热空穴应力导致的漏电流具有更加显著的瞬态特性.研究结果表明:热空穴SILC机制是由于氧化层空穴的退陷阱效应和正电荷辅助遂穿中心的湮没.利用热电子注入技术,正电荷辅助隧穿电流可被大大地减弱.     

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and V_h degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.     

超深亚微米PMOS器件的NBTI退化机理

对超深亚微米PMOS器件的负栅压温度不稳定性(NBTI)退化机理进行了研究.主要集中在对器件施加NBT和随后的PBT应力后器件阈值电压的漂移上.实验证明反型沟道中空穴在栅氧中的俘获以及氢分子在栅氧中的扩散是引起NBTI退化的主要原因.当应力条件变为PBT时，陷落的空穴可以快速退陷，但只有部分氢分子可以扩散回栅氧与衬底界面钝化硅悬挂键，这就导致了PBT条件下阈值电压只能部分恢复. 关键词： 超深亚微米PMOS器件 负偏压温度不稳定性 界面陷阱 氢气     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.     

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability (NBTI) has become one of the most serious reliability problems of metal- oxide-semiconductor field-effect transistors (MOSFETs). The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H+ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H+ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H+ generated during NBTI stress.     

Study on the recovery of NBTI of ultra-deep sub-micro MOSFETs

Taking the actual operating condition of complementary metal oxide semiconductor (CMOS) circuit into account, conventional direct current (DC) stress study on negative bias temperature instability (NBTI) neglects the detrapping of oxide positive charges and the recovery of interface states under the `low' state of p-channel metal oxide semiconductor field effect transistors (MOSFETs) inverter operation. In this paper we have studied the degradation and recovery of NBTI under alternating stress, and presented a possible recovery mechanism. The three stages of recovery mechanism under positive bias are fast recovery, slow recovery and recovery saturation.     

闪速存储器中应力诱生漏电流的产生机理

通过实验研究了闪速存储器存储单元中应力诱生漏电流(SILC)的产生机理. 研究结果表明，在低电场应力下，其可靠性问题主要是由载流子在氧化层里充放电引起，而在高电场下，陷阱和正电荷辅助的隧穿效应导致浮栅电荷变化是引起闪速存储器失效的主要原因. 分别计算了高场应力和低场应力两种情况下SILC中的稳态电流和瞬态电流的大小. 关键词： 闪速存储器 应力诱生漏电流 电容耦合效应 可靠性     

Dependence of short channel length on negative/positive bias temperature instability (NBTI/PBTI) for 3D FinFET devices

A comprehensive study of the negative and positive bias temperature instability(NBTI/PBTI)of 3D FinFET devices with different small channel lengths is presented.It is found while with the channel lengths shrinking from 100 nm to 30 nm,both the NBTI characteristics of p-FinFET and PBTI characteristics of n-FinFET turn better.Moreover,the channel length dependence on NBTI is more serious than that on PBTI.Through the analysis of the physical mechanism of BTI and the simulation of 3-D stress in the FinFET device,a physical mechanism of the channel length dependence on NBTI/PBTI is proposed.Both extra fluorine passivation in the corner of bulk oxide and stronger channel stress in p-FinFETs with shorter channel length causes less NBTI issue,while the extra nitrogen passivation in the corner of bulk oxide induces less PBTI degradation as the channel length decreasing for n-FinFETs.The mechanism well matches the experimental result and provides one helpful guide for the improvement of reliability issues in the advanced FinFET process.     

Mechanism of NBTI Recovery under Negative Voltage Stress

Recovery phenomenon is observed under negative gate voltage stress which is smaller than the previous degradation stress. We focus on the drain current to study the degradation and recovery of negative bias temperature instability (NBTI) with a real-time method. By this method, different recovery phenomena among different size devices are observed. Under negative recovery stress, the drain current gradually recovers for the large size devices and gets into recovery saturation when long recovery time is involved. For small-size devices, a step-like recovery of drain current is observed. The recovery of the drain current is mainly caused by the holes detrapping and tunnelling back to the channel surface which are trapped in oxide. The model of hole detrapping explains the recovery under negative voltage stress reasonably.     

Evaluation of negative bias temperature instability in ultra-thin gate oxide pMOSFETs using a new on-line PDO method

A new on-line methodology is used to characterize the negative bias temperature instability (NBTI) without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by I_D-V_D characterizations, which were measured before stress, and after every certain stress phase, using the proportional differential operator (PDO) method. The new on-line methodology avoids the mobility linearity assumption as compared with the previous on-the-fly method. It is found that both reaction--diffusion and charge-injection processes are important in NBTI effect under either DC or AC stress. A similar activation energy, 0.15 eV, occurred in both DC and AC NBTI processes. Also degradation rate factor is independent of temperature below 90\du\ and sharply increases above it. The frequency dependence of NBTI degradation shows that NBTI degradation is independent of frequencies. The carrier tunnelling and reaction--diffusion mechanisms exist simultaneously in NBTI degradation of sub-micron pMOSFETs, and the carrier tunnelling dominates the earlier NBTI stage and the reaction--diffusion mechanism follows when the generation rate of traps caused by carrier tunnelling reaches its maximum.     

Self-assembled formation of uniform InP nanopore arrays by electrochemical anodization in HCl based electrolyte

Attempts were made to optimize the electrochemical anodization process for the formation of high-density, regular and straight nanopore arrays on InP. The structure, shape and size of the pores were very sensitive to substrate orientations, electrolyte concentrations and anodization voltages. Among (1 1 1)A, (1 1 1)B and (0 0 1) substrate orientations, the most uniform and most straight nanopore arrays were obtained on (0 0 1) substrates at anodization voltages of 5-7 V by using 1.0-1.5 M HCl electrolyte containing HNO₃. The pore depth could be controlled up to 80 μm by the anodization time.     

Characterization of multilayered piezoelectric ceramics for high power transducers

In some circumstances, large vibrational displacements at ultrasonic frequency must be generated using a low voltage drive. This result cannot be obtained with monolithic PZT ceramics which require voltages larger than 1000 V to produce displacements of the micrometer order at resonance. The use of multilayered hard lead zirconate titanate ceramics as transduction material in resonant devices is experimentally investigated for Langevin-type transducers. Large amplitudes are obtained under low drive (5 microm under 10 V). Material constant (compliance, losses) variations under large dynamic stress are, at least, one order of magnitude larger than for monolithic ceramics. Depolarization is found to be a critical issue when the transducer is driven continuously. It is demonstrated that this problem can be solved by polishing the interfaces between different parts of the device and applying an electrical DC bias to the transducer.     

Surface modification of exchange-coupled Co/NiOx magnetic bilayer by bias sputtering

We have investigated the effect of bias voltage on sheet resistance, surface roughness and surface coverage of Co/NiO_x magnetic bilayer. In addition, interface topography and corrosion resistance of the Ta/Co/Cu/Co/NiO_x/Si(1 0 0) system have been studied for Co layers deposited at an optimum bias voltage. Atomic force microscopy (AFM) and four point probe sheet resistance (R_s) measurement have been used to determine surface and electrical properties of the sputtered Co layer at different bias voltages ranging from 0 to −80 V. The Co/NiO_x bilayer exhibits a minimum surface roughness and low sheet resistance value with a maximum surface coverage at V_b=−60 V resulted in a slight increase of magnetic resistance and its sensitivity for the Co/Cu/Co/NiO_x/Si(1 0 0) magnetic multilayers, as compared with the same magnetic multilayers containing unbiased Co layers. The presence of Ta protection layer improves the corrosion resistance of the multilayers by three orders of magnitude in a humid environment.     

The role of hydrogen in negative bias temperature instability of pMOSFET

The NBTI degradation phenomenon and the role of hydrogen during NBT stress are presented in this paper. It is found that PBT stress can recover a fraction of V_th shift induced by NBTI. However, this recovery is unstable. The original degradation reappears soon after reapplication of the NBT stress condition. Hydrogen-related species play a key role during a device's NBT degradation. Experimental results show that the diffusion species are neutral, they repassivate Si dangling bond which is independent of the gate voltage polarity. In addition to the diffusion towards gate oxide, hydrogen diffusion to Si-substrate must be taken into account for it also has important influence on device degradation during NBT stress.     

The switch of the worst case on NBTI and hot-carrier reliability for 0.13 μm pMOSFETs

This investigation describes experiments on two sizes of p-channel metal-oxide-semiconductor field-effect-transistors (pMOSFETs), to study the negative bias temperature instability (NBTI) and hot-carrier (HC) induced degradation. This work demonstrates that the worst condition for pMOSFETs under HC tests occurs in CHC (channel HC, stressed at V_g = V_d) mode at high temperature. This study also shows that the worst degradation of pMOSFETs should occur in NBTI. This inference is based on a comparison of results for forward saturation current (I_ds,f) and reverse saturation current (I_ds,r) obtained in NBTI and HC tests.     

人体静电放电对有机发光二极管的影响

研究了静电放电（ESD）人体模式（HBM）下的脉冲应力对有机发光二极管（OLED）的性能及寿命的影响,并讨论了相应的物理机制。对比分析了4组OLED在施加ESD放电为0,200,800,1 600 V前后的电学和光学特性,并进行了相应的寿命测试分析。研究发现,OLED器件的光谱对ESD不敏感,随着冲击电压的增大,由于静电打击对载流子的短期抑制效应,OLED的亮度出现轻微下降。在静电冲击电压为200 V和800 V时,伏安特性没有发生变化;当静电冲击电压增至1 600 V时,反向漏电有明显增加。后续的加速寿命实验表明,静电打击对器件的工作寿命没有明显的规律性影响,但是会一定程度提高非本质老化失效的概率。     

Piezoelectric non-linearity in PbSc0.5Ta0.5O3 thin films

Epitaxial (001)-oriented PbSc_0.5Ta_0.5O₃ (PST) thin films were deposited by pulsed laser deposition. Local piezoelectric investigations performed by piezoelectric force microscopy show a dual slope for the piezoelectric coefficient. A piezoelectric coefficient of 3 pm/V was observed at voltages up to 0.8 V. However, at voltages above 0.8 V, there is a steep increase in piezoelectric coefficient mounting to 23.2 pm/V. This nonlinear piezoelectric response was observed to be irreversible in nature. In order to better understand this nonlinear behavior, voltage dependent dielectric constant measurements were performed. These confirmed that the piezoelectric non-linearity is indeed a manifestation of a dielectric non-linearity. In contrast to classical ferroelectric systems, the observed dielectric non-linearity in this relaxor material cannot be explained by the Rayleigh model. Thus the dielectric non-linearity in the PST films is tentatively explained as a manifestation of a percolation of the polar nano regions.