考虑通孔效应和边缘传热效应的纳米级互连线温度分布模型

提出了同时考虑通孔效应和边缘传热效应的互连线温度分布模型,获得了适用于单层互连线和多层互连线温度分布的解析模型,并基于65 nm互补金属氧化物半导体（CMOS）工艺参数计算了不同长度单层互连线和多层互连线的温度分布.对于单层互连线,考虑通孔效应后中低层互连线的温升非常低,而全局互连线几乎不受通孔效应的影响,温升仍然很高.对于多层互连线,最上层互连线的温升最高,温升和互连介质层厚度近似成正比,而且互连介质材料热导率越低,温升越高.所提出的互连线温度分布模型,能应用于纳米级CMOS计算机辅助设计. 关键词： 通孔效应 边缘传热效应 纳米级互连线 温度分布模型     

A novel analytical thermal model for multilevel nano-scale interconnects considering the via effect

Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65~nm complementary metal oxide semiconductor (CMOS) process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design (CAD) of very large-scale integrated circuits (VLSIs) in nano-scale technologies.     

A multilevel nano-scale interconnection RLC delay model

Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit,this paper proposes a multilevel nano-scale interconnection RLC delay model with the method of numerical analysis,the proposed analytical model has summed up the influence of the configuration of multilevel interconnections,the via heat transfer and self-heating effect on the interconnection delay,which is closer to the actual situation.Delay simulation results show that the proposed model has high precision within 5% errors for global interconnections based on the 65 nm CMOS interconnection and material parameter,which can be applied in nanometer CMOS system chip computer-aided design.     

A novel low-swing interconnect optimization model with delay and bandwidth constraints

Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits.Based on the RLC interconnect delay model,by wire sizing,wire spacing and adopting low-swing interconnect technology,this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously.The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor(CMOS) interconnect parameters.The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process.The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.     

一种考虑温度的分布式互连线功耗模型

基于集总式电阻-电容树形功耗模型,考虑了非均匀温度分布对互连线电阻的影响,提出了一种新的分布式互连线动态功耗解析模型,解决了集总式模型不能表征非均匀温度变化带来的电阻变化的问题,并计算了一次非理想的激励冲激下整个互连模型消耗的总能量.基于所提出的分布式互连线功耗模型,计算了纳米级互补金属氧化物半导体（CMOS）工艺典型长度互连线的Elmore延时和功耗,发现非均匀温度分布对互连功耗的影响随着互连线长度的增加而增加,单位长度功耗随着CMOS工艺特征尺寸的变化而基本不变.文中所提出的功耗模型可以用来精确估算互 关键词： 互连线 温度梯度 动态功耗模型 纳米级互补金属氧化物半导体     

一种基于纳米级CMOS工艺的互连线串扰RLC解析模型

基于纳米级CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了分布式RLC耦合互连解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下提出了受扰线远端的数值表达式. 基于90和65 nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在4%内,能应用于纳米级片上系统（SOC）的电子设计自动化（EDA）设计和集成电路优化设计. 关键词： 纳米级CMOS 互连串扰 分布式 RLC解析模型')" href="#">RLC解析模型     

Simultaneous dual mode add/drop multiplexers for optical interconnects buses

For the potential realization of optical interconnect scheme based on modal diversity, we propose and analyze efficient mode add drop multiplexers (MADM). Each of the two types of MADM proposed here enables a simultaneous two channels (modes) add/drop to/from a multimode bus. The simultaneous operation is of importance in reducing the device footprint within the expected ultra-dense interconnects schemes. We developed analytical design rules for the adiabatic devices and verified by simulation that an implementation based on Silicon over Insulator waveguides, is exhibiting low loss and low channels crosstalk (below −22 dB).     

一种基于延时和带宽约束的纳米级互连线优化模型

基于RLC互连线延时模型,通过缓冲器插入和改变互连线宽及线间距,提出了一种基于延时和带宽约束的互连功耗-缓冲器面积的乘积优化模型.基于90 nm,65 nm和45 nm CMOS工艺验证了互连线优化模型,在牺牲1/3和1/2的带宽的前提下,平均能够节省46%和61%的互连功耗,以及65%和83%的缓冲器面积,能应用于纳米级SOC的计算机辅助设计. 关键词： 纳米互连功耗 缓冲器面积 延时 带宽     

考虑温度分布效应的非对称RLC树时钟偏差研究

提出了一种RLC互连树零时钟偏差构建方法.给出了RLC互连温度非均匀分布及其延时的解析公式,并推导计算了最优的零时钟偏差点,所提模型同时考虑了互连温度非均匀分布、电感效应及不对称互连结构对零时钟偏差点的影响.针对65 nm工艺节点对所提模型进行了仿真验证,结果显示,相较于同类模型,最大误差不超过1%. 关键词： RLC')" href="#">RLC 温度分布 不对称互连结构 零时钟偏差点     

临近空间单粒子串扰的解析模型

随着尺寸不断缩减, 串扰对单粒子效应的影响越来越重要. 为了量化串扰效应对单粒子瞬态(SET)的影响, 基于SET等效电路和互连线的6 结点模型, 利用所定义的导纳的四种规则, 简化计算, 推导了单粒子串扰(SEC)的解析模型. 通过求导和泰勒公式, 导出了串扰电压峰值的表达式. 仿真结果显示, 该解析模型与SPICE电路的一致性较好, 平均相对误差为2.51%, 最大误差为5.11%.     

Cryogenically Cooled CMOS

The factors affecting the feasibility of cryogenically cooled CMOS are reviewed. This approach becomes more attractive as CMOS feature sizes shrink below 250?nm where chip performance is limited by interconnect characteristics. The impact of interconnects is demonstrated using a methodology for estimating interconnect-limited CMOS performance. The cryogenic behavior of normal and superconducting interconnects is reviewed. Cooling the best normal interconnect metals such as Al or Cu to 77?K can produce 9×lower resistivity. High-temperature superconductors can produce lower resistance at GHz clock frequencies, but would be difficult to produce on low dielectric substrates compatible with silicon technology. Performance doubling has been demonstrated for CMOS circuits operating at liquid nitrogen temperature. Comparable performance improvements may be expected down to below 100?nm if process technology is adjusted appropriately. In addition, dramatic increases in DRAM storage times result from exponential decreases in subthreshold leakage currents. Circuit reliability should increase correspondingly, apart from hot-carrier induced degradation. Thermally efficient packages and refrigerators are required for cryogenic CMOS. Microchannel heat exchangers can produce thermally efficient cryogenic packages. However, thermodynamic limits to refrigerator performance may make operation at higher cryogenic temperatures more attractive.     

A novel interconnect-optimal repeater insertion model with target delay constraint in 65nm CMOS

Repeater optimization is the key for SOC (System on Chip) interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint. Based on the 65 nanometre CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines, and the better performance will be achieved with the longer line. The results compared with the reference paper demonstrate the validity of this model. It can be integrated into repeater design methodology and CAD (computer aided design) tool for interconnect planning in nanometre SOC.     

A statistical RCL interconnect delay model taking account of process variations

As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.     

Systematic study on the mechanical and electric behaviors of the nonbuckling interconnect design of stretchable electronics

Recently, we developed a nonbuckling interconnect design that provides an effective approach to simultaneously achieving high elastic stretchability, easiness for encapsulation, and high electric performance for stretchable electronics. This paper aims to systematically study its mechanical and electric behaviors, including comparisons of the nonbuckling and buckling interconnect designs on stretchability, effects of the thickness on electric performance, and modeling and experimental investigations on the finite deformation mechanics. It is found that the results on stretchability depend on the layouts. Long straight segments and small arc radii for nonbuckling interconnects yield an enhancement of stretchability, which is much better than that of buckling designs. On the other hand, shorter straight segments or thicker interconnects are better to lower the resistances of interconnects.Therefore, optimization of the designs needs to balance the requirements of both the mechanical and electric performances. The finite deformation of interconnects during stretching is analyzed. The established analytic model is well validated by both the finite element modeling and experimental investigations. This work is key for providing the design guidelines for nonbucklingbased stretchable electronics.     

一种基于多目标约束的互连线宽和线间距优化模型

优化线宽和线间距已经成为改善系统芯片性能的关键技术.本文基于互连线线宽和线间距对互连延时、功耗、面积和带宽的影响,提出了基于多目标优化方法实现优化线宽和线间距的思路,并利用曲线拟合方法得到了多目标约束的解析模型.Hspice验证结果显示,该解析模型精度较高,平均误差不超过5%,算法简单,能有效弥补应用品质因数方法的缺陷,可以应用于纳米级互补金属氧化物半导体系统芯片的计算机辅助设计.     

Coherent crosstalk in passive microring based Optical Networks-on-Chip

Optical Networks-on-Chip (ONoC) is emerging technology for future optical interconnects used in all optical networks. The electrical interconnects face lot of problems due to their inability to support higher data rates used in the System-on-Chip (SoC) technologies. Integrated optical interconnects based on SoC avoid this bottleneck with their support to higher data rates. In this paper for the first time we have studied and analyzed ONoC at physical level for the system performance based on crosstalk, BER, throughput, system frequency, and other related parameters. The investigation of ONoC performance is carried out for the multistage microring optical crossconnect on SoC for coherent WDM signals. The analysis can be used in the design of ultra-high speed photonic routers for reliable data communication and processing. The results show the dependency of a coherent crosstalk on the system frequency of SoC and also illustrate the reduction in throughput with increase in number of WDM signals due to higher probability of packet transmission. Minimum 2 dB signal to noise ratio can be obtained when crosstalk is ?25 dB with 60 wavelengths for probability of packet transmission is 0.5.     

Thermal effect analysis on crosstalk and performance of optoelectronic transmitter modules for optical interconnects

This paper presents thermal analysis on crosstalk and performance of optoelectronic transmitter modules and also demonstrates the thermal analysis for efficient heat dissipation for the transmitter modules. The thermal crosstalk model for analysis is based on interconnects parameters for vertically stacked and horizontally packaged optoelectronic transmitter modules. While the analytical expression is used to estimate the thermal critical frequency, f _{crit_th} , above which signals become severely deteriorated, a Teflon-based thermal printed circuit board (PCB) has been designed for packaging the optoelectronic transmitter modules to ensure efficient heat dissipation. The thermal and performance analysis of the packaged modules show that the chips operate at temperatures below the f _{crit_th} , which is apt for reliable data and signal transmission.     

Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits

Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.     

考虑通孔和边缘效应的互连网络热电分析

考虑互连通孔和边缘效应,建立互连层间、层内、通孔热阻模型,利用热电二元性,提出一种考虑温度效应对热流影响的热电耦合仿真方法,利用热电之间的反馈关系,修正建模后的温度分布对节点网络热流的影响.并对以聚合物和硅氧化物为介质的多层互连进行分析,以有限元建模结果为参照,与已有模型相比,互连热分布结果的相对标准差分别降低了71.2%、12.9%.考虑通孔效应和边缘效应后,该方法在不同纳米级工艺中所得峰值温升,较已有模型均有一定程度的降低.     

基于S域RLC传输线模型的多芯片组件互连功耗计算

为了分析多芯片组件的互连功耗,用RLC传输线模型对多芯片组件的互连进行表征,通过对输入互连的电流及其等效电阻的近似,推导出多芯片组件互连功耗的频域数学表达式,给出计算机仿真试验结果,对方法的有效性进行验证.