排序方式: 共有27条查询结果,搜索用时 15 毫秒
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Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits.Based on the RLC interconnect delay model,by wire sizing,wire spacing and adopting low-swing interconnect technology,this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously.The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor(CMOS) interconnect parameters.The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process.The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip. 相似文献
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Parasitic effects of air-gap through-silicon vias in high-speed three-dimensional integrated circuits 下载免费PDF全文
In this paper,ground-signal-ground type through-silicon vias(TSVs) exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-circuit model and passive elements(RLGC) parameters based on the physical parameters are presented with the frequency up to 100 GHz.The parasitic capacitance of TSVs can be approximated as the dielectric capacitance of air gaps when the thickness of air gaps is greater than 0.75 μm.Therefore,the applied voltage of TSVs only needs to achieve the flatband voltage,and there is no need to indicate the threshold voltage.This is due to the small permittivity of air gaps.The proposed model shows good agreement with the simulation results of ADS and Ansoft's HFSS over a wide frequency range. 相似文献
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提出了同时考虑通孔效应和边缘传热效应的互连线温度分布模型,获得了适用于单层互连线和多层互连线温度分布的解析模型,并基于65 nm互补金属氧化物半导体(CMOS)工艺参数计算了不同长度单层互连线和多层互连线的温度分布.对于单层互连线,考虑通孔效应后中低层互连线的温升非常低,而全局互连线几乎不受通孔效应的影响,温升仍然很高.对于多层互连线,最上层互连线的温升最高,温升和互连介质层厚度近似成正比,而且互连介质材料热导率越低,温升越高.所提出的互连线温度分布模型,能应用于纳米级CMOS计算机辅助设计.
关键词:
通孔效应
边缘传热效应
纳米级互连线
温度分布模型 相似文献
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硅通孔(TSV)是三维集成电路的一种主流技术.基于TSV寄生参数提取模型,对不同物理尺寸的TSV电阻-电容(RC)参数进行提取,采用Q3D仿真结果验证了模型精度.分析TSVRC效应对片上系统的性能及功耗影响,推导了插入缓冲器的三维互连线延时与功耗的解析模型.在45nm互补金属氧化物半导体工艺下,对不同规模的互连电路进行了比较分析.模拟结果显示,TSVRC效应导致互连延时平均增加10%,互连功耗密度平均提高21%;电路规模越小,TSV影响愈加显著.在三维片上系统前端设计中,包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能. 相似文献
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文章研究了GaN基共振隧穿二极管 (RTD) 的退化现象. 通过向AlGaN/GaN/AlGaN量子阱中引入三个实测的深能级陷阱中心并自洽求解薛定谔方程和泊松方程, 计算并且讨论了陷阱中心对GaN基RTD的影响. 结果表明, GaN基RTD的退化现象是由陷阱中心的缺陷密度和激活能的共同作用引起. 由于陷阱中心的电离率和激活能的指数呈正相关关系, 因此具有高激活能的陷阱中心俘获更多电子, 对负微分电阻 (NDR) 特性的退化起主导作用.
关键词:
共振隧穿二极管
GaN
陷阱中心
电离率 相似文献
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Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits 下载免费PDF全文
Through-silicon-via (TSV) to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits (3D ICs). Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively. 相似文献
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