一种基于延时和带宽约束的纳米级互连线优化模型

基于RLC互连线延时模型,通过缓冲器插入和改变互连线宽及线间距,提出了一种基于延时和带宽约束的互连功耗-缓冲器面积的乘积优化模型.基于90 nm,65 nm和45 nm CMOS工艺验证了互连线优化模型,在牺牲1/3和1/2的带宽的前提下,平均能够节省46%和61%的互连功耗,以及65%和83%的缓冲器面积,能应用于纳米级SOC的计算机辅助设计. 关键词： 纳米互连功耗 缓冲器面积 延时 带宽     

An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.     

An Interconnect Bus Power Optimization Method

A simple yet accurate interconnect parasitical capacitance model is presented. Based on this model a novel interconnect bus optimization methodology is proposed. Combining wire spacing with wire ordering, this methodology focuses on bus dynamic power optimization with consideration of bus performance requirements. The optimization methodology is verified under a 65 nm technology node and it shows that with 50% slack in the routing space, a 33.039% power saving can be provided by the proposed optimization methodology for an intermediate video bus compared to the 27.68% power saving provided by uniform spacing technology. The proposed methodology is especially suitable for computer-aided design of nanometer scale on-chip buses.     

A novel interconnect-optimal repeater insertion model with target delay constraint in 65nm CMOS

Repeater optimization is the key for SOC (System on Chip) interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint. Based on the 65 nanometre CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines, and the better performance will be achieved with the longer line. The results compared with the reference paper demonstrate the validity of this model. It can be integrated into repeater design methodology and CAD (computer aided design) tool for interconnect planning in nanometre SOC.     

考虑自热效应的互连线功耗优化模型

基于互连线的分布式功耗模型,考虑自热效应的同时采用非均匀互连线结构,提出了一种基于延时、带宽、面积、最小线宽和最小线间距约束的互连动态功耗优化模型.分别在90和65 nm互补金属氧化物半导体工艺节点下验证了功耗优化模型的有效性,在工艺约束下同时不牺牲延时、带宽和面积所提模型能够降低高达35％互连线功耗.该模型适用于片上网络构架中大型互连路由结构和时钟网络优化设计.     

An RLC interconnect analyzable crosstalk model considering self-heating effect

According to the thermal profile of actual multilevel interconnects, in this paper we propose a temperature distribution model of multilevel interconnects and derive an analytical crosstalk model for the distributed resistance-inductance-capacitance (RLC) interconnect considering effect of thermal profile. According to the 65-nm complementary metal-oxide semiconductor (CMOS) process, we compare the proposed RLC analytical crosstalk model with the Hspice simulation results for different interconnect coupling conditions and the absolute error is within 6.5%. The computed results of the proposed analytical crosstalk model show that RCL crosstalk decreases with the increase of current density and increases with the increase of insulator thickness. This analytical crosstalk model can be applied to the electronic design automation (EDA) and the design optimization for nanometer CMOS integrated circuits.     

考虑非均匀温度分布效应的缓冲器插入最优尺寸研究

基于非均匀温度分布效应对互连延时的影响, 提出了一种求解互连非均匀温度分布情况下的缓冲器最优尺寸的模型. 给出了非均匀温度分布情况下的RC互连延时解析表达式, 通过引入温度效应消除因子, 得出了最优插入缓冲器尺寸以使互连总延时最优. 针对90 nm和65 nm工艺节点, 对所提模型进行了仿真验证, 结果显示, 相较于以往同类模型, 本文所提模型由于考虑了互连非均匀温度分布效应, 更加准确有效, 且在保证互连延时最优的情况下有效地提高了芯片面积的利用.     

一种基于纳米级CMOS工艺的互连线串扰RLC解析模型

基于纳米级CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了分布式RLC耦合互连解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下提出了受扰线远端的数值表达式. 基于90和65 nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在4%内,能应用于纳米级片上系统（SOC）的电子设计自动化（EDA）设计和集成电路优化设计. 关键词： 纳米级CMOS 互连串扰 分布式 RLC解析模型')" href="#">RLC解析模型     

考虑互连温度分布的缓冲器插入延时优化方法

针对VLSI设计中存在的互连电感效应、热电耦合以及互连温度分布的问题,提出一种缓冲器插入延时优化方法.首先根据互连温度分布的特点得出其电阻模型和延时模型,通过延时、功耗和温度之间的热电耦合效应求得考虑互连温度分布的缓冲器插入最优化延时,利用Matlab软件求得最佳优化结果.采用该方法针对45 nm工艺节点的缓冲器插入进行分析和验证,证实了方法的有效性.研究表明,忽略互连电感效应会高估芯片的优化延时,忽略互连温度分布会低估芯片的优化延时,在全局互连尺寸较小(线宽为245 nm)时,忽略互连温度分布会低估互连延时8.71%.     

A statistical RCL interconnect delay model taking account of process variations

As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.     

考虑通孔效应和边缘传热效应的纳米级互连线温度分布模型

提出了同时考虑通孔效应和边缘传热效应的互连线温度分布模型,获得了适用于单层互连线和多层互连线温度分布的解析模型,并基于65 nm互补金属氧化物半导体（CMOS）工艺参数计算了不同长度单层互连线和多层互连线的温度分布.对于单层互连线,考虑通孔效应后中低层互连线的温升非常低,而全局互连线几乎不受通孔效应的影响,温升仍然很高.对于多层互连线,最上层互连线的温升最高,温升和互连介质层厚度近似成正比,而且互连介质材料热导率越低,温升越高.所提出的互连线温度分布模型,能应用于纳米级CMOS计算机辅助设计. 关键词： 通孔效应 边缘传热效应 纳米级互连线 温度分布模型     

一种基于多目标约束的互连线宽和线间距优化模型

优化线宽和线间距已经成为改善系统芯片性能的关键技术.本文基于互连线线宽和线间距对互连延时、功耗、面积和带宽的影响,提出了基于多目标优化方法实现优化线宽和线间距的思路,并利用曲线拟合方法得到了多目标约束的解析模型.Hspice验证结果显示,该解析模型精度较高,平均误差不超过5%,算法简单,能有效弥补应用品质因数方法的缺陷,可以应用于纳米级互补金属氧化物半导体系统芯片的计算机辅助设计.     

A multilevel nano-scale interconnection RLC delay model

Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit,this paper proposes a multilevel nano-scale interconnection RLC delay model with the method of numerical analysis,the proposed analytical model has summed up the influence of the configuration of multilevel interconnections,the via heat transfer and self-heating effect on the interconnection delay,which is closer to the actual situation.Delay simulation results show that the proposed model has high precision within 5% errors for global interconnections based on the 65 nm CMOS interconnection and material parameter,which can be applied in nanometer CMOS system chip computer-aided design.     

基于RLCπ型等效模型的互连网络精确焦耳热功耗计算

基于互连网络的RLC π型等效模型,考虑电感的屏蔽作用和非理想的阶跃激励,提出了互连线网络在斜阶跃激励下的焦耳热功耗计算方法,极大地简化了互连网络中电流和功耗的表达式. 基于90 nm金属氧化物半导体(CMOS)工艺的互连参数对所提出的计算方法进行了计算和仿真验证,对于上升信号小于1 ns的情况,计算结果与Hspice仿真结果的误差小于3%,具有很高的精度,适合应用于大规模互连网络中的功耗估算和热分析.     

一种考虑温度的分布式互连线功耗模型

基于集总式电阻-电容树形功耗模型,考虑了非均匀温度分布对互连线电阻的影响,提出了一种新的分布式互连线动态功耗解析模型,解决了集总式模型不能表征非均匀温度变化带来的电阻变化的问题,并计算了一次非理想的激励冲激下整个互连模型消耗的总能量.基于所提出的分布式互连线功耗模型,计算了纳米级互补金属氧化物半导体（CMOS）工艺典型长度互连线的Elmore延时和功耗,发现非均匀温度分布对互连功耗的影响随着互连线长度的增加而增加,单位长度功耗随着CMOS工艺特征尺寸的变化而基本不变.文中所提出的功耗模型可以用来精确估算互 关键词： 互连线 温度梯度 动态功耗模型 纳米级互补金属氧化物半导体     

基于双电源电压和双阈值电压的全局互连性能优化

基于双电源电压和双阈值电压技术,提出了一种优化全局互连性能的新方法.文中首先定义了一个包含互连延时、带宽和功耗等因素的品质因子用以描述全局互连特性,然后在给定延时牺牲的前提下,通过最大化品质因子求得优化的双电压数值用以节省功耗.仿真结果显示,在65 nm工艺下,针对5%,10%和20%的允许牺牲延时,所提方法相较于单电压方法可分别获得27.8%,40.3%和56.9%的功耗节省.同时发现,随着工艺进步,功耗节省更加明显.该方法可用于高性能全局互连的优化和设计. 关键词： 全局互连 双电源电压 双阈值电压 功耗     

考虑温度分布效应的非对称RLC树时钟偏差研究

提出了一种RLC互连树零时钟偏差构建方法.给出了RLC互连温度非均匀分布及其延时的解析公式,并推导计算了最优的零时钟偏差点,所提模型同时考虑了互连温度非均匀分布、电感效应及不对称互连结构对零时钟偏差点的影响.针对65 nm工艺节点对所提模型进行了仿真验证,结果显示,相较于同类模型,最大误差不超过1%. 关键词： RLC')" href="#">RLC 温度分布 不对称互连结构 零时钟偏差点     

Three-dimensional global interconnect based on a design window

Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit (3D IC) is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip (SOC) is established by evaluating the constraints of 1) wiring resource, 2) wiring bandwidth, and 3) wiring noise. In comparison to a two-dimensional integrated circuit (2D IC) in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.     

An Optimized Three-Level Design of Decoder Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) has been potentially considered as a supersede to Complementary Metal–Oxide–Semiconductor (CMOS) because of its inherent advantages. Many QCA-based logic circuits with smaller feature size, improved operating frequency, and lower power consumption than CMOS have been offered. This technology works based on electron relations inside quantum-dots. Due to the importance of designing an optimized decoder in any digital circuit, in this paper, we design, implement and simulate a new 2-to-4 decoder based on QCA with low delay, area, and complexity. The logic functionality of the 2-to-4 decoder is verified using the QCADesigner tool. The results have shown that the proposed QCA-based decoder has high performance in terms of a number of cells, covered area, and time delay. Due to the lower clock pulse frequency, the proposed 2-to-4 decoder is helpful for building QCA-based sequential digital circuits with high performance.     

一种非均匀线型的互连线能量分布模型

基于互连线信号传输微分方程,推导非均匀互连线的电压和电流分布表达式,根据实际情况,考虑非理性激励提出包括前端驱动和后端负载的二端口非均匀互连电路各部分能量分布表达式.基于65 nm CMOS工艺参数,对方法进行计算仿真验证,计算结果与Hspice仿真结果比较误差小于5%,具有很高的精度.该方法适用于高性能全局互连的前端优化设计分析.