Study of 4H-SiC junction barrier Schottky diode using field guard ring termination

This paper reports that the 4H-SiC Schottky barrier diode, PiN diode and junction barrier Schottky diode terminated by field guard rings are designed, fabricated and characterised. The measurements for forward and reverse characteristics have been done, and by comparison with each other, it shows that junction barrier Schottky diode has a lower reverse current density than that of the Schottky barrier diode and a higher forward drop than that of the PiN diode. High-temperature annealing is presented in this paper as well to figure out an optimised processing. The barrier height of 0.79 eV is formed with Ti in this work, the forward drop for the Schottky diode is 2.1 V, with an ideality factor of 3.2, and junction barrier Schottky diode with blocking voltage higher than 400 V was achieved by using field guard ring termination.     

Improvements in reverse breakdown characteristics of THz GaAs Schottky barrier varactor based on metal–brim structure

The excellent reverse breakdown characteristics of Schottky barrier varactor(SBV) are crucially required for the application of high power and high efficiency multipliers. The SBV with a novel Schottky structure named metal–brim is fabricated and systemically evaluated. Compared with normal structure, the reverse breakdown voltage of the new type SBV improves from -7.31V to -8.75V. The simulation of the Schottky metal–brim SBV is also proposed. Three factors,namely distribution of leakage current, the electric field, and the area of space charge region are mostly concerned to explain the physical mechanism. Schottky metal–brim structure is a promising approach to improve the reverse breakdown voltage and reduce leakage current by eliminating the accumulation of charge at Schottky electrode edge.     

Design consideration and fabrication of 1.2-kV 4H-SiC trenched-and-implanted vertical junction field-effect transistors

We present the design consideration and fabrication of 4H-SiC trenched-and-implanted vertical junction field-effect transistors （TI-VJFETs）. Different design factors, including channel width, channel doping, and mesa height, are con- sidered and evaluated by numerical simulations. Based on the simulation result, normally-on and normally-off devices are fabricated. The fabricated device has a 12 μm thick drift layer with 8 × 10^15 cm^-3 N-type doping and 2.6 μm channel length. The normally-on device shows a 1.2 kV blocking capability with a minimum on-state resistance of 2.33 mΩ.cm2, while the normally-off device shows an on-state resistance of 3.85 mΩ.cm2. Both the on-state and the blocking performances of the device are close to the state-of-the-art values in this voltage range.     

Trapezoid mesa trench metal-oxide semiconductor barrier Schottky rectifier: an improved Schottky rectifier with better reverse characteristics

An improved structure of Schottky rectifier,called a trapezoid mesa trench metal-oxide semiconductor (MOS) barrier Schottky rectifier (TM-TMBS),is proposed and studied by two-dimensional numerical simulations.Both forward and especially better reverse I-V characteristics,including lower leakage current and higher breakdown voltage,are demonstrated by comparing our proposed TM-TMBS with a regular trench MOS barrier Schottky rectifier (TMBS) as well as a conventional planar Schottky barrier diode rectifier.Optimized device parameters corresponding to the requirement for high breakdown voltage are given.With optimized parameters,TM-TMBS attains a breakdown voltage of 186 V,which is 6.3% larger than that of the optimized TMBS,and a leakage current of 4.3×10 6 A/cm 2,which is 26% smaller than that of the optimized TMBS.The relationship between optimized breakdown voltage and some device parameters is studied.Explanations and design rules are given according to this relationship.     

High-performance 4H-SiC junction barrier Schottky diodes with double resistive termination extensions

4H-SiC junction barrier Schottky (JBS) diodes with a high-temperature annealed resistive termination extension (HARTE) are designed, fabricated and characterized in this work. The differential specific on-state resistance of the device is as low as 3.64 m ·cm2 with a total active area of 2.46×10-3 cm2 . Ti is the Schottky contact metal with a Schottky barrier height of 1.08 V and a low onset voltage of 0.7V. The ideality factor is calculated to be 1.06. Al implantation annealing is performed at 1250℃ in Ar, while good reverse characteristics are achieved. The maximum breakdown voltage is 1000 V with a leakage current of 9×10-5 A on chip level. These experimental results show good consistence with the simulation results and demonstrate that high-performance 4H-SiC JBS diodes can be obtained based on the double HARTE structure.     

Investigations on mesa width design for 4H–SiC trench super junction Schottky diodes

Mesa width(WM) is a key design parameter for SiC super junction(SJ) Schottky diodes(SBD) fabricated by the trench-etching-and-sidewall-implant method. This paper carries out a comprehensive investigation on how the mesa width design determines the device electrical performances and how it affects the degree of performance degradation induced by process variations. It is found that structures designed with narrower mesa widths can tolerant substantially larger charge imbalance for a given BV target, but have poor specific on-resistances. On the contrary, structures with wider mesa widths have superior on-state performances but their breakdown voltages are more sensitive to p-type doping variation. Medium WMstructures(～ 2 μm) exhibit stronger robustness against the process variation resulting from SiC deep trench etching.Devices with 2-μm mesa width were fabricated and electrically characterized. The fabricated SiC SJ SBDs have achieved a breakdown voltage of 1350 V with a specific on-resistance as low as 0.98 m?·cm~2. The estimated specific drift onresistance by subtracting substrate resistance is well below the theoretical one-dimensional unipolar limit of SiC material.The robustness of the voltage blocking capability against trench dimension variations has also been experimentally verified for the proposed SiC SJ SBD devices.     

Modeling of 4H--SiC multi-floating-junction Schottky barrier diode

This paper develops a new and easy to implement analytical model for the specific on-resistance and electric field distribution along the critical path for 4H-SiC multi-floating junction Schottky barrier diode. Considering the charge compensation effects by the multilayer of buried opposite doped regions, it improves the breakdown voltage a lot in comparison with conventional one with the same on-resistance. The forward resistance of the floating junction Schottky barrier diode consists of several components and the electric field can be understood with superposition concept, both are consistent with MEDICI simulation results. Moreover, device parameters are optimized and the analyses show that in comparison with one layer floating junction, multilayer of floating junction layer is an effective way to increase the device performance when specific resistance and the breakdown voltage are traded off. The results show that the specific resistance increases 3.2 mΩ·cm 2 and breakdown voltage increases 422 V with an additional floating junction for the given structure.     

Comparison of electrical characteristic between AlN/GaN and AlGaN/GaN heterostructure Schottky diodes

Ni/Au Schottky contacts on AlN/GaN and AlGaN/GaN heterostructures are fabricated.Based on the measured current–voltage and capacitance–voltage curves,the electrical characteristics of AlN/GaN Schottky diode,such as Schottky barrier height,turn-on voltage,reverse breakdown voltage,ideal factor,and the current-transport mechanism,are analyzed and then compared with those of an AlGaN/GaN diode by self-consistently solving Schrdinger’s and Poisson’s equations.It is found that the dislocation-governed tunneling is dominant for both AlN/GaN and AlGaN/GaN Schottky diodes.However,more dislocation defects and a thinner barrier layer for AlN/GaN heterostructure results in a larger tunneling probability,and causes a larger leakage current and lower reverse breakdown voltage,even though the Schottky barrier height of AlN/GaN Schottky diode is calculated to be higher that of an AlGaN/GaN diode.     

Enhancement of Breakdown Voltage in AlGaN/GaN High Electron Mobility Transistors Using Double Buried p-Type Layers

A novel AlGaN/GaN high electron mobility transistor(HEMT) with double buried p-type layers(DBPLs) in the GaN buffer layer and its mechanism are studied.The DBPL AlGaN/GaN HEMT is characterized by two equi-long p-type GaN layers which are buried in the GaN buffer layer under the source side.Under the condition of high-voltage blocking state,two reverse p-n junctions introduced by the buried p-type layers will effectively modulate the surface and bulk electric fields.Meanwhile,the buffer leakage is well suppressed in this structure and both lead to a high breakdown voltage.The simulations show that the breakdown voltage of the DBPL structure can reach above 2000 V from 467 V of the conventional structure with the same gate-drain length of 8μm.     

Comparison of electrical characteristic between AIN/GaN and AIGaN/GaN heterostructure Schottky diodes

Ni/Au Schottky contacts on A1N/GaN and A1GaN/GaN heterostructures are fabricated. Based on the measured current-voltage and capacitance-voltage curves, the electrical characteristics of AlN/GaN Schottky diode, such as Schottky barrier height, turn-on voltage, reverse breakdown voltage, ideal factor, and the current-transport mechanism, are analyzed and then compared with those of an A1GaN/GaN diode by self-consistently solving Schrodinger＇s and Poisson＇s equations. It is found that the dislocation-governed tunneling is dominant for both AlN/GaN and AlGaN/GaN Schottky diodes. However, more dislocation defects and a thinner barrier layer for AlN/GaN heterostrncture results in a larger tunneling probability, and causes a larger leakage current and lower reverse breakdown voltage, even though the Schottky barrier height of AlN/GaN Schottky diode is calculated to be higher that of an A1GaN/GaN diode.     

结终端采用JTE保护技术的4H-SiC PiN二极管模拟和研制

利用二维器件模拟软件ISE-TCAD 10.0,对结终端采用结扩展保护技术的4H-SiC PiN二极管平面器件进行反向耐压特性的模拟,并获得许多有价值的模拟数据.依据所得的模拟数据进行此种二极管器件的研制.实验测试表明,此二极管的模拟优化数据与实验测试的结果一致性较好,4H-SiC PiN二极管所测得到的反向电压达1600 V,该反向耐压数值达到理想平面结的击穿耐压90%以上.     

电荷耦合效应对高耐压沟槽栅极超势垒整流器击穿电压的影响

通过沟槽结构和可调节的电子势垒,沟槽栅极超势垒整流器可以更为有效地实现通态压降和反向漏电流之间的良好折衷.在高压应用时,电荷耦合效应对于提高该器件的反向承压能力起到了关键作用.本文通过理论模型与器件模拟结果,分析了沟槽深度、栅氧厚度和台面宽度等关键参数对电荷耦合作用下二维电场分布的影响,归纳出了提高该器件击穿电压的思路与方法,为器件设计提供了有意义的指导.在此基础上,提出了阶梯栅氧结构,该结构在维持几乎相同击穿电压的同时,使正向导通压降降低51.49%.     

n,p柱宽度对超结SiGe功率二极管电学特性的影响

结合SiGe材料的优异性能与超结结构在功率器件方面的优势,提出了一种超结SiGe功率二极管.该器件有两个重要特点:一是由轻掺杂的p型柱和n型柱相互交替形成超结结构,取代传统功率二极管的n^-基区;二是阳极p⁺区采用很薄的应变SiGe材料.该二极管可以克服常规Si p⁺n^-n⁺功率二极管存在的一些缺陷,如阻断电压增大的同时,正向导通压降随之增大,反向恢复时间也变长.利用二维器件模拟软件MEDICI仿真 关键词： 超结 锗硅二极管 n p柱宽度 电学特性     

Hybrid-anode structure designed for a high-performance quasi-vertical GaN Schottky barrier diode

A quasi-vertical GaN Schottky barrier diode with a hybrid anode structure is proposed to trade off the on-resistance and the breakdown voltage. By inserting a SiN dielectric between the anode metal with a relatively small length, it suppresses the electric field crowding effect without presenting an obvious effect on the forward characteristics. The enhanced breakdown voltage is ascribed to the charge-coupling effect between the insulation dielectric layer and GaN. On the other hand, the current density is decreased beneath the dielectric layer with the increasing length of the SiN, resulting in a high on-resistance. Furthermore, the introduction of the field plate on the side wall forms an metal-oxide-semiconductor (MOS) channel and decreases the series resistance, but also shows an obvious electric field crowding effect at the bottom of the mesa due to the quasi-vertical structure.     

具有p-GaN岛状埋层耐压结构的横向AlGaN/GaN高电子迁移率晶体管

GaN基高电子迁移率晶体管(HEMT)相对较低的击穿电压严重限制了其大功率应用.为了进一步改善器件的击穿特性,通过在n-GaN外延缓冲层中引入六个等间距p-GaN岛掩埋缓冲层(PIBL)构成p-n结,提出一种基于p-GaN埋层结构的新型高耐压AlGaN/GaN HEMT器件结构.Sentaurus TCAD仿真结果表明,在关态高漏极电压状态下,p-GaN埋层引入的多个反向p-n结不仅能够有效调制PIBL AlGaN/GaN HEMT的表面电场和体电场分布,而且对于缓冲层泄漏电流有一定的抑制作用,这保证了栅漏间距为10μm的PIBL HEMT能够达到超过1700 V的高击穿电压(BV),是常规结构AlGaN/GaN HEMT击穿电压(580 V)的3倍.同时,PIBL结构AlGaN/GaN HEMT的特征导通电阻仅为1.47 m?·cm~2,因此获得了高达1966 MW·cm~(-2)的品质因数(FOM=BV~2/R_(on,sp)).相比于常规的AlGaN/GaN HEMT,基于新型p-GaN埋岛结构的HEMT器件在保持较低特征导通电阻的同时具有更高的击穿电压,这使得该结构在高功率电力电子器件领域具有很好的应用前景.     

Reverse blocking characteristics and mechanisms in Schottky-drain AlGaN/GaN HEMT with a drain field plate and floating field plates

In this paper, a novel Al Ga N/Ga N HEMT with a Schottky drain and a compound field plate(SD-CFP HEMT) is presented for the purpose of better reverse blocking capability. The compound field plate(CFP) consists of a drain field plate(DFP) and several floating field plates(FFPs). The physical mechanisms of the CFP to improve the reverse breakdown voltage and to modulate the distributions of channel electric field and potential are investigated by two-dimensional numerical simulations with Silvaco-ATLAS. Compared with the HEMT with a Schottky drain(SD HEMT) and the HEMT with a Schottky drain and a DFP(SD-FP HEMT), the superiorities of SD-CFP HEMT lie in the continuous improvement of the reverse breakdown voltage by increasing the number of FFPs and in the same fabrication procedure as the SD-FP HEMT.Two useful optimization laws for the SD-CFP HEMTs are found and extracted from simulation results. The relationship between the number of the FFPs and the reverse breakdown voltage as well as the FP efficiency in SD-CFP HEMTs are discussed. The results in this paper demonstrate a great potential of CFP for enhancing the reverse blocking ability in Al Ga N/Ga N HEMT and may be of great value and significance in the design and actual manufacture of SD-CFP HEMTs.     

具有纵向辅助耗尽衬底层的新型横向双扩散金属氧化物半导体场效应晶体管

为了优化横向双扩散金属氧化物半导体场效应晶体管(lateral double-diffused MOSFET,LDMOS)的击穿特性及器件性能,在传统LDMOS结构的基础上,提出了一种具有纵向辅助耗尽衬底层(assisted depletesubstrate layer,ADSL)的新型LDMOS.新加入的ADSL层使得漏端下方的纵向耗尽区大幅向衬底扩展,从而利用电场调制效应在ADSL层底部引入新的电场峰,使纵向电场得到优化,同时横向表面电场也因为电场调制效应而得到了优化.通过ISE仿真表明,当传统LDMOS与ADSL LDMOS的漂移区长度都是70μm时,击穿电压由462 V增大到897 V,提高了94%左右,并且优值也从0.55 MW/cm~2提升到1.24 MW/cm~2,提升了125%.因此,新结构ADSL LDMOS的器件性能较传统LDMOS有了极大的提升.进一步对ADSL层进行分区掺杂优化,在新结构的基础上,击穿电压在双分区时上升到938 V,三分区时为947 V.     

Deep SiC etching with RIE

SiC is currently an important topic in power devices. This new technology leads to lower power losses, faster switching, and higher working temperature. The design of SiC power devices requires the integration of edge termination techniques to obtain a high blocking voltage. The mesa structure approach is one well-established method. It could be used alone or in combination with a Junction Termination Extension (JTE). The mesa consists of a structure that removes material around the pn-junction. Due to the strong Si–C bonds, conventional chemical–wet etching solutions are inefficient on SiC, so plasma methods are required to etch SiC.The presented work is based on the use of an RIE reactor with an SF₆/ O₂ plasma. Its geometry structure and parameters were optimized. An etch rate of 0.35 μm/min was obtained without any trenching phenomenon. Trenches deeper than 10 μm deep were realized with a nickel etching mask that shows a high selectivity. AFM analysis revealed an etched surface as smooth as the initial one.     

A super-junction SOI-LDMOS with low resistance electron channel

A novel super-junction LDMOS with low resistance channel(LRC), named LRC-LDMOS based on the silicon-oninsulator(SOI) technology is proposed. The LRC is highly doped on the surface of the drift region, which can significantly reduce the specific on resistance(Ron,sp) in forward conduction. The charge compensation between the LRC, N-pillar,and P-pillar of the super-junction are adjusted to satisfy the charge balance, which can completely deplete the whole drift,thus the breakdown voltage(BV) is enhanced in reverse blocking. The three-dimensional(3 D) simulation results show that the BV and R_(on,sp) of the device can reach 253 V and 15.5 mΩ·cm~2, respectively, and the Baliga's figure of merit(FOM = BV~2/R_(on,sp)) of 4.1 MW/cm~2 is achieved, breaking through the silicon limit.