1200 V碳化硅功率MOSFET低温特性的实验表征及分析

碳化硅功率MOSFET是宽禁带功率半导体器件的典型代表,具有优异的电气性能。基于低温环境下的应用需求,研究了1200 V碳化硅功率MOSFET在77.7 K至300 K温区的静/动态特性,定性分析了温度对碳化硅功率MOSFET性能的影响。实验结果显示,温度从300 K降低至77.7 K时,阈值电压上升177.24%,漏-源极击穿电压降低32.99%,栅极泄漏电流降低82.51%,导通电阻升高1142.28%,零栅压漏电流降低89.84%(300 K至125 K)。双脉冲测试显示,开通时间增大8.59%,关断时间降低16.86%,开关损耗增加48%。分析发现,碳化硅功率MOSFET较高的界面态密度和较差的沟道迁移率,是导致其在低温下性能劣化的主要原因。     

Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.     

高功率窄脉宽半导体激光激励器设计

为了获得高功率窄脉宽半导体激光,设计了半导体激光器相应的激励单元,论述MOSFET作为高速开关的工作机理,分析基于MOSFET作为高速开关产生窄的大电流脉冲的电路模型.为了使MOSFET开关速度尽可能快,根据前述分析,提出推挽式MOSFET栅极驱动方式并设计了触发窄脉冲的发生电路.当激光二极管接入放电回路时,实验表明:激光二极管输出光的峰值功率可达67.5 W,脉宽约为20 ns.最后,简要分析了影响光脉冲宽度的因素.     

纳米尺度MOSFET过剩噪声的定性分析

最近实验表明纳米尺度MOSFET中的过剩噪声主要为散粒噪声,而此前研究认为MOSFET中不存在散粒噪声,短沟道MOSFET中的过剩噪声为热噪声. 本文基于器件电流模型分析散粒噪声取代热噪声成为过剩噪声主要成分的转变条件,根据该条件对纳米尺度MOSFET噪声特性的预测与文献报道的实验现象、模拟结果以及介观散粒噪声相关结论相符合. 关键词： 散粒噪声 过剩噪声 纳米尺度MOSFET     

Investigation of laterally single-diffused metal oxide semiconductor (LSMOS) field effect transistor

We propose a distinct approach to implement a laterally single diffused metal-oxide-semiconductor (LSMOS) FET with only one impurity doped p-n junction. In the LSMOS, a single p-n junction is first created using lateral dopant diffusion. The channel is formed in the p region of the p-n junction and the n region acts as the drift region. Two distinct metals of different work function are used to form the “n⁺” source/drain regions and “p⁺” body contact using the charge plasma concept. We demonstrate that the LSMOS is similar in performance to a laterally double diffused metal-oxide-semiconductor (LDMOS) although it has only one impurity doped p-n junction. The LSMOS exhibits a breakdown voltage of ∼50.0 V, an average ON-resistance of 48.7 mΩ-mm² and a peak transconductance of 53.6 μS/μm similar to that of a comparable LDMOS.     

Study of a 4H-SiC epitaxial n-channel MOSFET

Epitaxial channel metal-oxide semiconductor field-effect transistors (MOSFETs) have been proposed as one possible way to avoid the problem of low inversion layers in traditional MOSFETs. This paper presents an equation of maximum depletion width modified which is more accurate than the original equation. A 4H--SiC epitaxial n-channel MOSFET using two-dimensional simulator ISE is simulated. Optimized structure would be realized based on the simulated results for increasing channel mobility.     

One-dimensional continuous analytic potential solution to generic oxide-silicon-oxide system

A one-dimensional continuous analytic potential solution to a generic oxide--silicon--oxide system is developed. With the analytic solution, the potential distribution in the silicon film is predicted. A physics-based relation between surface potentials is also derived and then applied to the generic oxide--silicon--oxide metal--oxide--semiconductor field-effect transistors (MOSFETs) for the calculation of surface potentials     

Heat transfer enhancement in MOSFET mounted on different FR4 substrates by thermal transient measurement

Miniaturization of electronic package leads to high heat density and heat accumulation in electronics device, resulting in short life time and premature failure of the device. Junction temperature and thermal resistance are the critical parameters that determine the thermal management and reliability in electronics cooling. Metal oxide field effect transistor (MOSFET) is an important semiconductor device for light emitting diode-integrated circuit (LED IC) driver application, and thermal management in MOSFET is a major challenge. In this study, investigations on thermal performance of MOSFET are performed for evaluating the junction temperature and thermal resistance. Suitable modifications in FR4 substrates are proposed by introducing thermal vias and copper layer coating to improve the thermal performance of MOSFET. Experiments are conducted using thermal transient tester (T3ster) at 2.0 A input current and ambient temperature varying from 25 ℃to 75 °C. The thermal parameters are measured for three proposed designs: FR4 with circular thermal vias, FR4 with single strip of copper layer and embedded vias, and FR4 with I-shaped copper layer, and compared with that of plain FR4 substrate. From the experimental results, FR4_I-shaped shows promising results by 33.71% reduction in junction temperature and 54.19% reduction in thermal resistance. For elevated temperature, the relative increases in junction temperature and thermal resistance are lower for FR4_I-shaped than those for other substrates considered. The introduction of thermal vias and copper layer plays a significant role in thermal performance.     

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain(LDD) overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.     

A compact I－V model for lightly-doped-drain MOSFETs

A novel model for lightly-doped-drain (LDD) MOSFETs is proposed, which utilizes the empirical hyperbolic tangent function to describe the I－V characteristics. The model includes the strong inversion and subthreshold mechanism, and shows a good prediction for submicron LDD MOSFET. Moreover, the model requires low computation time consumption and is suitable for design of MOSFETs devices and circuits.