A novel high performance TFS SJ IGBT with a buried oxide layer

A novel high performance trench field stop(TFS) superjunction(SJ) insulated gate bipolar transistor(IGBT) with a buried oxide(BO) layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT(Conv-SJ), the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop(Vce(on)) and an improved tradeoff between Vce(on)and turn-off loss(Eoff), with no breakdown voltage(BV) degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5 μm and Nn = Np = 3 × 1015cm-3, the Vce(on)and Eoffof the proposed structure are 1.08 V and 2.81 mJ/cm2with the collector doping concentration Nc = 1×1018cm-3and 1.12 V and1.73 mJ/cm2with Nc = 5 × 1017cm-3, respectively. However, with the same device parameters, the Vce(on)and Eofffor the Conv-SJ are 1.81 V and 2.88 mJ/cm2with Nc = 1 × 1018cm-3and 1.98 V and 2.82 mJ/cm2with Nc = 5 × 1017cm-3,respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.     

Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO₂ than SiO₂ in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, I_ON/I_OFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO₂, DIBL shows a reduction of 61.5% over SiO₂. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO₂ when compared to SiO₂. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO₂ based device. From the analysis, it is found that HfO₂ will be a better alternative for the future nanoscale device.     

Enhanced interface properties of diamond MOSFETs with Al_2O_3 gate dielectric deposited via ALD at a high temperature

The interface state of hydrogen-terminated(C–H) diamond metal–oxide–semiconductor field-effect transistor(MOSFET) is critical for device performance. In this paper, we investigate the fixed charges and interface trap states in C–H diamond MOSFETs by using different gate dielectric processes. The devices use Al_2O_3 as gate dielectrics that are deposited via atomic layer deposition(ALD) at 80℃ and 300℃, respectively, and their C–V and I–V characteristics are comparatively investigated. Mott–Schottky plots(1/C~2–VG) suggest that positive and negative fixed charges with low density of about 1011 cm~(-2) are located in the 80-℃-and 300-℃ deposition Al_2O_3 films, respectively. The analyses of direct current(DC)/pulsed I–V and frequency-dependent conductance show that the shallow interface traps(0.46 e V–0.52 e V and0.53 e V–0.56 e V above the valence band of diamond for the 80-℃ and 300-℃ deposition conditions, respectively) with distinct density(7.8 × 10~(13) e V~(-1)·cm~(-2)–8.5 × 10~(13) e V-1·cm~(-2) and 2.2 × 1013 e V~(-1)·cm~(-2)–5.1 × 10~(13) e V~(-1)·cm~(-2) for the80-℃-and 300-℃-deposition conditions, respectively) are present at the Al_2O_3/C–H diamond interface. Dynamic pulsed I–V and capacitance dispersion results indicate that the ALD Al_2O_3 technique with 300-℃ deposition temperature has higher stability for C–H diamond MOSFETs.     

0.18 μm MOSFET器件的总剂量辐照效应

对0.18 μm metal-oxide-semiconductor field-effect-transistor (MOSFET)器件进行γ射线辐照实验,讨论分析器件辐照前后关态漏电流、阈值电压、跨导、栅电流、亚阈值斜率等特性参数的变化,研究深亚微米器件的总剂量效应. 通过在隔离氧化物中引入等效陷阱电荷,三维模拟结果与实验结果符合很好. 深亚微米器件栅氧化层对总剂量辐照不敏感,浅沟槽隔离氧化物是导致器件性能退化的主要因素. 关键词： 总剂量效应 浅沟槽隔离 氧化层陷阱正电荷 MOSFET     

A Passband-Flattened EDG Demultiplexer with an Air-Trenched Taper

A novel passband flattening method for a planar waveguide demultiplexer based on an etched diffraction grating is presented. A strongly confined taper is formed by etching air trenches at both sides of the input waveguide. The geometric parameters of the taper are optimized by considering the figure of merit, ripple, and loss. Numerical simulation for a design example is given to illustrate the passband flattening method.     

不同散射机理对 Al2O3/InxGa1-xAs nMOSFET 反型沟道电子迁移率的影响

通过考虑体散射、界面电荷的库仑散射以及 Al₂O₃/In_xGa_1-xAs 界面粗糙散射等主要散射机理, 建立了以 Al₂O₃为栅介质In_xGa_1-xAs n 沟金属-氧化物-半导体场效应晶体管 (nMOSFETs) 反型沟道电子迁移率模型, 模拟结果与实验数据有好的符合. 利用该模型分析表明, 在低至中等有效电场下, 电子迁移率主要受界面电荷库仑散射的影响; 而在强场下, 电子迁移率则取决于界面粗糙度散射. 降低界面态密度, 减小 Al₂O₃/In_xGa_1-xAs 界面粗糙度, 适当提高In含量并控制沟道掺杂在合适值是提高 InGaAs nMOSFETs 反型沟道电子迁移率的主要途径. 关键词： InGaAs MOSFET 反型沟道电子迁移率 散射机理     

非对称HALO掺杂栅交叠轻掺杂漏围栅MOSFET的解析模型

为抑制短沟道效应和热载流子效应, 提出了一种非对称HALO掺杂栅交叠轻掺杂漏围栅MOSFET新结构. 通过在圆柱坐标系中精确求解三段连续的泊松方程, 推导出新结构的沟道静电势、阈值电压以及亚阈值电流的解析模型. 结果表明, 新结构可有效抑制短沟道效应和热载流子效应, 并具有较小的关态电流. 此外, 分析还表明栅交叠区的掺杂浓度对器件的亚阈值电流几乎没有影响, 而栅电极功函数对亚阈值电流的影响较大. 解析模型结果和三维数值仿真工具ISE所得结果高度符合.     

深亚微米器件沟道长度对总剂量辐照效应的影响

研究了180 nm 互补金属氧化物半导体技术下的器件沟道长度对总剂量辐照效应的影响. 在其他条件如辐照偏置、器件结构等不变的情况下, 氧化层中的陷阱电荷决定了辐照响应. 浅沟槽隔离氧化层中的陷阱电荷使得寄生的侧壁沟道反型, 从而形成大的关态泄漏电流. 这个电流与沟道长度存在一定的关系, 沟道长度越短, 泄漏电流越大. 首次发现辐照会增强这个电流的沟道长度调制效应, 从而使得器件进一步退化.     

高迁移率In0.6Ga0.4As沟道MOSHEMT与MOSFET器件特性的研究

从模拟和实验两个方面对高迁移率In_0.6Ga_0.4As沟道金属氧化物半导体高电子迁移率晶体管（MOSHEMT）和金属氧化物半导体场效应晶体管（MOSFET）器件开展研究工作.研宄发现InAlAs势垒层对Ino_0.6Ga_0.4AsMOSHEMT的特性具有重要影响.与Ino_0.6Ga_0.4As MOSFET相比,Ino_0.6Ga_0.4As MOSHEMT表现出优异的电学特性.实验结果表明,In_0.6Ga_0.4As MOSHEMT的有效沟道迁移率达到2812 cm²/V.s^-1,是In_0.6Ga_0.4As MOSFET的3.2倍.0.02 mm栅长的MOSHEMT器件较相同栅长的MOSFET器件具有更高的驱动电流、更大的跨导峰值、更大的开关比、更高的击穿电压和更小的亚阈值摆幅.