基区Ge组分分布对SiGe HBTs热学特性的影响

基区Ge组分的加入可以改善SiGe HBT的直流特性、 频率特性和噪声特性, 但Ge组分及其分布对HBT热学特性的影响报道还很少. 本文利用SILVACO半导体器件仿真工具, 建立了多指SiGe HBT模型, 对基区具有不同Ge组分梯度结构的SiGe HBTs的热学特性和电学特性的热稳定性进行了研究. 研究发现, 在Ge组分总量一定的条件下, 随着Ge组分梯度的增大, 器件的特征频率明显提高, 增益β和特征频率f_T随温度变化变弱, 器件温度分布的均匀性变好, 但增益变小; 而基区均匀Ge组分(Ge组分梯度为零) 的HBT的增益较大, 但随温度的变化较大, 器件温度分布的均匀性也较差. 在此基础上, 将基区Ge组分均匀分布和Ge组分缓变分布相结合, 提出了兼顾器件热学特性、 增益特性和频率特性的新型基区Ge组分分布- 分段分布结构. 结果表明, 相比于基区Ge组分均匀分布的器件, 新器件温度明显降低; β和f_T保持了较高的值, 且随温度的变化也较小, 显示了新结构器件的优越性. 这些结果对HBT的热学设计具有重要的参考意义, 是对SiGe HBT性能研究的一个补充.     

能带工程对射频功率SiGe异质结双极晶体管热性能的改善

众所周知,基区"能带工程"可以改善Si_1-xGe _{x 基区异质结双极晶体管(HBT)的直流、频率和噪声等特性,但"能带工程"对HBT热学特性的影响的研究还很少。本文基于三维热电反馈模型,分析了"能带工程"对射频功率SiGe HBT热性能的影响。考虑到电流增益随温度的变化以及发射结电压负温度系数,给出了器件热稳定所需最小镇流电阻(REmin)的表达式,在此基础上给出了非均匀镇流电阻的设计,进一步提高了SiGe HBT的热稳定性 关键词： SiGe HBT Ge组分 热电反馈 镇流电阻}     

采用发射极非均匀指间距技术改善功率异质结双极晶体管热稳定性的研究

为了提高多发射极功率异质结双极晶体管的热稳定性,本文利用耦合热阻表征发射极指间距变化对发射极指间热耦合作用的影响,得到了耦合热阻与发射极指间距之间的变化关系,提出了发射极非均匀指间距技术.通过热电反馈模型对采用发射极非均匀指间距技术的功率HBT进行热稳定性分析,得到了多发射极指上的温度分布.结果表明,多发射极HBT在采用非均匀发射极指间距技术后,峰值温度明显下降,温度变化幅度更加平缓,有效地提高了器件的热稳定性. 关键词： 异质结双极晶体管 耦合热阻 指间距     

Ge组分分布对基区杂质非均匀分布的SiGe HBT温度特性的影响

众所周知, 双极型晶体管的设计主要是基区的设计. 一般而言, 基区的杂质分布是非均匀的. 本文首先研究了非均匀的杂质高斯分布对器件温度分布、增益和截止频率的温度特性的影响, 发现增益和截止频率具有正温度系数, 体内温度较高. 随后研究了基区Ge组分分布对这些器件参数的影响. 均匀Ge组分分布和梯形Ge组分分布的SiGe 异质结双极型晶体管增益和截止频率具有负温度系数, 具有较好的体内温度分布. 进一步的研究表明, 具有梯形Ge组分分布的SiGe 异质结双极型晶体管, 由于Ge组分缓变引入了少子加速电场, 不但使它的增益和截止频率具有较高的值, 而且保持了较弱的温度敏感性, 在增益、特征频率大小及其温度敏感性、体内温度分布达到了很好的折中.     

含有本征SiGe层的SiGe异质结双极晶体管集电结耗尽层宽度模型

本文分别建立了含有本征SiGe层的SiGe HBT(异质结双极晶体管)集电结耗尽层各区域的电势、电场分布模型,并在此基础上,建立了集电结耗尽层宽度和延迟时间模型,对该模型进行了模拟仿真,定量地分析了SiGe HBT物理、电学参数对集电结耗尽层宽度和延迟时间的影响,随着基区掺杂浓度和集电结反偏电压的提高,集电结耗尽层延迟时间也随之增大,而随着集电区掺杂浓度的提高和基区Ge组分增加,集电结耗尽层延迟时间随之减小. 关键词： SiGe HBT 集电结耗尽层 延迟时间     

多孔介质中非等温互溶流体驱替过程的格子Boltzmann研究

利用格子Boltzmann方法,在孔隙尺度上对多孔介质内非等温混溶驱替过程进行数值研究,定量分析温度粘性膨胀系数（β_T）以及路易斯数（Le）对界面不稳定性和驱替效率的影响.结果表明：随着β_T的增大,界面不稳定性增强,驱替效率降低.当β_T>0时,随着Le的增大,界面不稳定性减弱,驱替流体与被驱替流体之间的界面趋于平缓,指尖残余率减小,驱替效率增大.当β_T<0时,Le对于驱替效率的影响相反.     

功率AlGaAs/GaAs HBT自加热频率特性

提出了一种功率AlGaAs/GaAs HBT的自加热温度模型,讨论了在大电流条件下,器件晶格温度升高和基区扩展效应对HBT器件频率特性的影响,并对器件的晶格温度、截止频率和最高振荡频率在自加热条件下的变化分别进行了计算和模拟.     

多晶SiGe栅量子阱pMOSFET阈值电压模型

本文基于多晶SiGe栅量子阱SiGe pMOSFET器件物理,考虑沟道反型时自由载流子对器件纵向电势的影响,通过求解泊松方程,建立了p+多晶SiGe栅量子阱沟道pMOS阈值电压和表面寄生沟道开启电压模型.应用MATLAB对该器件模型进行了数值分析,讨论了多晶Si_1-yGe_y栅Ge组分、Si_1-xGe_x量子阱沟道Ge组分、栅氧化层厚度、Si帽层厚度、沟道区掺杂浓度和 关键词： 多晶SiGe栅 寄生沟道 量子阱沟道 阈值电压     

重离子导致的锗硅异质结双极晶体管单粒子效应电荷收集三维数值模拟

针对国产锗硅异质结双极晶体管(SiGe HBTs), 采用半导体器件模拟工具, 建立SiGe HBT单粒子效应三维损伤模型, 研究影响SiGe HBT单粒子效应电荷收集的关键因素. 分析比较重离子在不同位置入射器件时, 各电极的电流变化和感生电荷收集情况, 确定SiGe HBT电荷收集的敏感区域. 结果表明, 集电极/衬底结内及附近区域为集电极和衬底收集电荷的敏感区域, 浅槽隔离内的区域为基极收集电荷的敏感区域, 发射极收集的电荷可以忽略. 此项工作的开展为下一步采用设计加固的方法提高器件的抗辐射性能打下了良好的基础. 关键词： 锗硅异质结双极晶体管 单粒子效应 电荷收集 三维数值仿真     

Thermal stability improvement of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations using non-uniform finger spacing

A method of non-uniform finger spacing is proposed to enhance thermal stability of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations. Temperature distribution on the emitter fingers of a multi-finger SiGe heterojunction bipolar transistor is studied using a numerical electro-thermal model. The results show that the SiGe heterojunction bipolar transistor with non-uniform finger spacing has a small temperature difference between fingers compared with a traditional uniform finger spacing heterojunction bipolar transistor at the same power dissipation. What is most important is that the ability to improve temperature non-uniformity is not weakened as power dissipation increases. So the method of non-uniform finger spacing is very effective in enhancing the thermal stability and the power handing capability of power device. Experimental results verify our conclusions.     

Designing power heterojunction bipolar transistors with non-uniform emitter finger lengths to achieve high thermal stability

With the aid of a thermal-electrical model,a practical method for designing multi-finger power heterojunction bipolar transistors with finger lengths divided in groups is proposed.The method can effectively enhance the thermal stability of the devices without sacrificing the design time.Taking a 40-finger heterojunction bipolar transistor for example,the device with non-uniform emitter finger lengths is optimized and fabricated.Both the theoretical and the experimental results show that,for the optimum device,the peak temperature is lowered by 26.19 K and the maximum temperature difference is reduced by 56.67% when compared with the conventional heterojunction bipolar transistor with uniform emitter finger length.Furthermore,the ability to improve the uniformity of the temperature profile and to expand the thermal stable operation range is strengthened as the power level increases,which is ascribed to the improvement of the thermal resistance in the optimum device.A detailed design procedure is also summarized to provide a general guide for designing power heterojunction bipolar transistors with non-uniform finger lengths.     

Thermal resistance matrix representation of thermal effects and thermal design in multi-finger power heterojunction bipolar transistors

The thermal resistance matrix including self-heating thermal resistance and thermal coupling resistance is presented to describe the thermal effects of multi-finger power heterojunction bipolar transistors. The dependence of thermal resistance matrix on finger spacing is also investigated. It is shown that both self-heating thermal resistance and thermal coupling resistance are lowered by increasing the finger spacing, in which the downward dissipated heat path is widened and the heat flow from adjacent fingers is effectively suppressed. The decrease of self-heating thermal resistance and thermal coupling resistance is helpful for improving the thermal stability of power devices. Furthermore, with the aid of the thermal resistance matrix, a 10-finger power heterojunction bipolar transistor (HBT) with non-uniform finger spacing is designed for high thermal stability. The optimized structure can effectively lower the peak temperature while maintaining a uniformity of the temperature profile at various biases and thus the device effectively may operate at a higher power level.     

Three-dimensional simulation of fabrication process-dependent effects on single event effects of SiGe heterojunction bipolar transistor

The fabrication process dependent effects on single event effects(SEEs) are investigated in a commercial silicon–germanium heterojunction bipolar transistor(SiGe HBT) using three-dimensional(3D) TCAD simulations. The influences of device structure and doping concentration on SEEs are discussed via analysis of current transient and charge collection induced by ions strike. The results show that the SEEs representation of current transient is different from representation of the charge collection for the same process parameters. To be specific, the area of C/S junction is the key parameter that affects charge collection of SEE. Both current transient and charge collection are dependent on the doping of collector and substrate. The base doping slightly influences transient currents of base, emitter, and collector terminals. However, the SEEs of SiGe HBT are hardly affected by the doping of epitaxial base and the content of Ge.     

Effect of lateral structure parameters of SiGe HBTs on synthesized active inductors

The effect of lateral structure parameters of transistors including emitter width, emitter length, and emitter stripe number on the performance parameters of the active inductor(AI), such as the effective inductance Ls, quality factor Q,and self-resonant frequency ω_0 is analyzed based on 0.35-μm Si Ge Bi CMOS process. The simulation results show that for AI operated under fixed current density JC, the HBT lateral structure parameters have significant effect on Ls but little influence on Q and ω_0, and the larger Ls can be realized by the narrow, short emitter stripe and few emitter stripes of Si Ge HBTs. On the other hand, for AI with fixed HBT size, smaller JCis beneficial for AI to obtain larger Ls, but with a cost of smaller Q and ω_0. In addition, under the fixed collector current IC, the larger the size of HBT is, the larger Ls becomes, but the smaller Q and ω_0 become. The obtained results provide a reference for selecting geometry of transistors and operational condition in the design of active inductors.     

A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

The product of the cutoff frequency and breakdown voltage( fT×BVCEO) is an important figure of merit(FOM) to characterize overall performance of heterojunction bipolar transistor(HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator(SOI) Si Ge HBT to simultaneously improve the FOM of fT×BVCEOand thermal stability is presented by using two-dimensional(2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness(TBOX) on fT, BVCEO, and the FOM of fT×BVCEOare presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEOto some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT,BVCEO, and the FOM of fT×BVCEOcan be improved by increasing SOI insulator Si O_2 layer thickness TBOXin SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of Si O_2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEOis improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer into collector region provides an effective method to improve SOI Si Ge HBT overall performance.