Fabrication of Ge-channel MOSFETs by using replacement gate process and selective epitaxial growth

We fabricated Ge-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) by using replacement gate process and selective epitaxial growth. In our method, thin Ge layers were selectively grown on the channel region of MOSFETs after the removal of a sacrificial gate stack structure and the etching of the channel region. Ge layers with a smooth surface and a good morphology could be obtained by using the thin Si_0.5Ge_0.5 buffer layer. Dislocations were observed in the epitaxial layers and near the interface between the epitaxial layer and the substrates. We consider that these dislocations degrade the device performance. Although the electrical characteristics of the obtained MOSFETs need further improvement, our method is one of the promising candidates for the practical fabrication process of Ge-channel MOSFETs.     

The study on two-dimensional analytical model for gate stack fully depleted strained Si on silicon-germanium-on-insulator MOSFETs

Based on the exact resultant solution of two-dimensional Poisson's equation in strained Si and Si_{1 - X}Ge_X layer, a simple and accurate two-dimensional analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator (SGOI) MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects (SCE), the drain-induced barrier-lowering (DIBL) and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.     

Self-aligned metal-SiO2-InP based MISFETS having modulation doped channels

A novel metal-SiO₂-InP MISFET (metal-insulator-semiconductor field effect transistor) structure is proposed. This device incorporates a modulation doped channel and the self-aligned gate feature of Si MOSFETs. The modulation doping provides very high electron mobility and the self-alignment of gate, source and drain provides high packing density. Analytical results on current-voltage and transconductance characteristics are presented. Significant enhancement in high frequency performance over conventional MISFETs, employing SiO₂ as an insulator, is reported.     

Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson’s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.     

Physics of fluctuation processes in downscaled silicon MOSFETs

Physical mechanics of fluctuation processes in advanced submicron and decananometer MOSFETs (metal-oxide-semiconductor field-effect transistors) including the ultra-thin film SOI (siliconon-insulator) devices using strained silicon films are reviewed. The review is substantially based on the results obtained by the authors. It is shown that the following drastic changes occur in the nature and parameters of noise in such devices as a result of their downscaling when the gate oxide thickness and the channel length and width are decreased, the SOI substrates are used, the silicon film thickness is reduced, the film doping level is varied, the strained silicon films are employed, etc. Firstly, the Lorentzian components can appear in the current noise spectra. Those components are due to (i) electron tunneling from the valence band through the gate oxide in the SOI MOSFETs of a sufficiently thin gate oxide (LKE-Lorentzians); (ii) Nyquist fluctuations generated in the source and drain regions near the back Si/SiO₂ interface in the SOI MOSFETs (BGI Lorentzians); (iii) electron exchange between the channel and some single trap in the gate oxide of the transistors with sufficiently small length and width of the channel (RTS Lorentzians). Secondly, the 1/f-noise level can increase due to (i) the appearance of recombination processes near the Si/SiO₂ interface activated by the currents of electron tunneling from the valence band; (ii) an increase in the trap density in the gate oxide of the devices fabricated on the biaxially tensile-strained silicon films; (iii) the contribution of the 1/f fluctuations of the current flowing through the gate oxide as a result of electron tunneling from the conduction band. At the same time, the 1/f-noise level may decrease due to a decrease in the trap density in the gate oxide of the transistors fabricated on the uniaxially tensile-strained silicon films. Moreover, a 1/f ^1.7 component may appear in the noise spectra for the transistors of a sufficiently thin gate oxide, whose component is due to charge fluctuations on the defects located near the interface between the gate polysilicon and the gate oxide.     

N/P沟道MOSFET1/f噪声的统一模型

对n／p两种沟道类型、不同沟道尺寸MOSFET的1／f噪声特性进行了实验和理论研究.实验结 果表明，虽然nMOSFET的1／f噪声幅值比pMOSFET大一个数量级，但是其噪声幅值均表现出和 有效栅压的平方成反比、和漏压的平方成正比、和沟道面积成反比的规律.基于该实验结果 ，认为MOSFET的1/f噪声产生机理为位于半导体_氧化物界面附近几个纳米范围内的氧化层陷 阱通过俘获和发射过程与沟道交换载流子，在引起载流子数涨落的同时也通过库仑散射导致 沟道载流子迁移率的涨落.在这两种涨落机理的基础上，引入了氧化层陷阱的分布特征及其 与沟道交换载流子的隧穿和热激活两种方式，建立了MOSFET l／f噪声的统一模型.实验结果 和本文模型符合良好. 关键词： 1/f噪声 MOSFET 氧化层陷阱 涨落     

Effect of interface roughness on the carrier transport in germanium MOSFETs investigated by Monte Carlo method

Interface roughness strongly influences the performance of germanium metal--organic--semiconductor field effect transistors (MOSFETs). In this paper, a 2D full-band Monte Carlo simulator is used to study the impact of interface roughness scattering on electron and hole transport properties in long- and short- channel Ge MOSFETs inversion layers. The carrier effective mobility in the channel of Ge MOSFETs and the in non-equilibrium transport properties are investigated. Results show that both electron and hole mobility are strongly influenced by interface roughness scattering. The output curves for 50~nm channel-length double gate n and p Ge MOSFET show that the drive currents of n- and p-Ge MOSFETs have significant improvement compared with that of Si n- and p-MOSFETs with smooth interface between channel and gate dielectric. The $82\%$ and $96\%$ drive current enhancement are obtained for the n- and p-MOSFETs with the completely smooth interface. However, the enhancement decreases sharply with the increase of interface roughness. With the very rough interface, the drive currents of Ge MOSFETs are even less than that of Si MOSFETs. Moreover, the significant velocity overshoot also has been found in Ge MOSFETs.     

A study of GaN MOSFETs with atomic-layer-deposited Al2O3 as the gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with atomic-layer-deposited Al₂O₃ gate dielectrics are fabricated. The device, with atomic-layer-deposited Al₂O₃ as the gate dielectric, presents a drain current of 260 mA/mm and a broad maximum transconductance of 34 mS/mm, which are better than those reported previously with Al₂O₃ as the gate dielectric. Furthermore, the device shows negligible current collapse in a wide range of bias voltages, owing to the effective passivation of the GaN surface by the Al₂O₃ film. The gate drain breakdown voltage is found to be about 59.5 V, and in addition the channel mobility of the n-GaN layer is about 380 cm²/Vs, which is consistent with the Hall result, and it is not degraded by atomic-layer-deposition Al₂O₃ growth and device fabrication.     

High temperature characteristics of ZnO-based MOS-FETs with a photochemical vapor deposition SiO2 gate dielectric

The authors report the fabrication of ZnO-based metal-oxide-semiconductor field effect transistors (MOSFETs) with a high quality SiO₂ gate dielectric by photochemical vapor deposition (photo-CVD) on a sapphire substrate. Compared with ZnO-based metal-semiconductor FETs (MESFETs), it was found that the gate leakage current was decreased to more than two orders of magnitude by inserting the photo-CVD SiO₂ gate dielectric between ZnO and gate metal. Besides, it was also found that the fabricated ZnO MOSFETs can achieve normal operation of FET, even operated at 150 °C. This could be attributed to the high quality of photo-CVD SiO₂ layer. With a 2 μm gate length, the saturated I_ds and maximum transconductance (G_m) were 61.1 mA/mm and 10.2 mS/mm for ZnO-based MOSFETs measured at room temperature, while 45.7 mA/mm and 7.67 mS/mm for that measured at 150 °C, respectively.     

Ultrathin gate dielectrics for silicon nanodevices

This paper reviews recent progress in structural and electronic characterizations of ultrathin SiO₂thermally grown on Si(100) surfaces and applications of such nanometer-thick gate oxides to advanced MOSFETs and quantum-dot MOS memory devices. Based on an accurate energy band profile determined for the n ⁺ -poly- Si/SiO₂/Si(100) system, the measured tunnel current through ultrathin gate oxides has been quantitatively explained by theory. From the detailed analysis of MOSFET characteristics, the scaling limit of gate oxide thickness is found to be 0.8 nm. Novel MOSFETs with a silicon quantum-dot floating gate embedded in the gate oxide have indicated the multiple-step electron injection to the dot, being interpreted in terms of Coulombic interaction among charged dots.     

Ge metal oxide semiconductor field effect transistors with optimized Si cap and HfSiO2 high-k metal gate stacks

High mobility metal-oxide-semiconductor-field-effect-transistors (MOSFETs) are demonstrated on high quality epitaxial Si_0.75Ge_0.25 films selectively grown on Si (100) substrates. With a Si cap processed on Si_0.75Ge_0.25 channels, HfSiO₂ high-k gate dielectrics exhibited low C–V hysteresis (<10 mV), interface trap density (7.5 × 10¹⁰), and gate leakage current (∼10⁻²A/cm² at an EOT of 13.4 Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the Si_0.75Ge_0.25 channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of Si_0.75Ge_0.25 channels, which are major causes of the high off-state current of small band gap energy Si_0.75Ge_0.25 pMOSFETs, by improving gate control over the channel.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

高k介质异质栅全耗尽SOI MOSFET二维解析模型

为了研究高介电常数(高k)栅介质材料异质栅中绝缘衬底上的硅和金属-氧化物-硅场效应晶体管的短沟道效应,为新结构器件建立了全耗尽条件下表面势和阈值电压的二维解析模型.模型中考虑了各种主要因素的影响,包括不同介电常数材料的影响,栅金属长度及其功函数变化的影响,不同漏电压对短沟道效应的影响.结果表明,沟道表面势中引入了阶梯分布,因此源端电场较强;同时漏电压引起的电势变化可以被屏蔽,抑制短沟道效应.栅介电常数增大,也可以较好的抑制短沟道效应.解析模型与数值模拟软件ISE所得结果高度吻合. 关键词： 异质栅 绝缘衬底上的硅 阈值电压 解析模型     

A study on the performance of metal-oxide-semiconductor-field-effect-transistors with asymmetric junction doping structure

Diode currents of MOSFET were studied and characterized in detail for the ion implanted pn junction of short channel MOSFETs with shallow drain junction doping structure. The diode current in MOSFET junctions was analyzed on the point of view of the gate-induced-drain leakage (GIDL) current. We could found the GIDL current is generated by the band-to-band tunneling (BTBT) of electrons through the reverse biased channel-to-drain junction and had good agreement with BTBT equation. The effect of the lateral electric field on the GIDL current according to the body bias voltage is characterized and discussed. We measured the electrical doping profiling of MOSFETs with a short gate length, ultra thin oxide thickness and asymmetric doped drain structure and checked the profile had good agreement with simulation result. An accurate effective mobility of an asymmetric source–drain junction transistor was successfully extracted by using the split C–V technique.     

Study of single event effect for the InP-based HEMT with In0.53Ga0.47As/In0.3Ga0.7As/In0.7Ga0.3As composite channel

In this study, the single event effects in In_0.53Ga_0.47As/In_0.3Ga_0.7As/In_0.7Ga_0.3As composite channel InP-based HEMT are investigated using TCAD simulation for the first time. Due to the higher conduction band difference between bottom In_0.7Ga_0.3As channel and InAlAs buffer, the electrons in the buffer layer induced by ions strike cannot enter the channel, led to reduce the peak concentration in the composite channel and significantly weakened the drain current for composite channel device. Meanwhile, higher barrier height under the gate for composite channel InP-based HEMT is formed after particle strike, and further attenuate the drain current. Therefore, the single event effects can be effectively reduced by designing channel structure. In addition, drain voltage and incident position also show significant impact drain current. With the increase in the drain voltage, the drain current increase and the most sensitive incident position is the gate electrode for the device.     

TEOS-based low-pressure chemical vapor deposition for gate oxides in 4H–SiC MOSFETs using nitric oxide post-deposition annealing

The use of SiO₂/4H–SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) can be problematic due to high interface state density (D_it) and low field-effect mobility (μ_fe). Here, we present a tetra-ethyl-ortho-silicate (TEOS)-based low-pressure chemical vapor deposition (LPCVD) method for fabricating the gate oxide of 4H–SiC MOSFETs using nitric oxide post-deposition annealing. SiO₂/4H–SiC MOS capacitors and MOSFETs were fabricated using conventional wet and TEOS oxides. The measured effective oxide charge density (Q_eff) and D_it of the TEOS-based LPCVD SiO₂/4H–SiC MOS capacitor with nitridation were 4.27 × 10¹¹ cm⁻² and 2.99 × 10¹¹ cm⁻²eV⁻¹, respectively. We propose that the oxide breakdown field and barrier height were dependent on the effective Q_eff. The measured μ_fe values of the SiO₂/4H–SiC MOSFETs with wet and TEOS oxides after nitridation were, respectively, 11.0 and 17.8 cm²/V due to the stable nitrided interface between SiO₂ and 4H–SiC. The proposed gate stack is suitable for 4H–SiC power MOSFETs.     

3D quantum mechanical simulation of square nanowire MOSFETs by using NEGF method

In order to investigate the specifications of nanoscale transistors, we have used a three dimensional (3D) quantum mechanical approach to simulate square cross section silicon nanowire (SNW) MOSFETs. A three dimensional simulation of silicon nanowire MOSFET based on self consistent solution of Poisson-Schrödinger equations is implemented. The quantum mechanical transport model of this work uses the non-equilibrium Green’s function (NEGF) formalism. First, we simulate a double-gate (DG) silicon nanowire MOSFET and compare the results with those obtained from nanoMOS simulation. We understand that when the transverse dimension of a DG nanowire is reduced to a few nanometers, quantum confinement in that direction becomes important and 3D Schrödinger equation must be solved. Second, we simulate gate-all-around (GAA) silicon nanowire MOSFETs with different shapes of gate. We have investigated GAA-SNW-MOSFET with an octagonal gate around the wire and found out it is more suitable than a conventional GAA MOSFET for its more I _on /I _off , less Drain-Induced-Barrier-Lowering (DIBL) and less subthreshold slope.     

稀土元素掺杂的Hf基栅介质材料研究进展

随着金属氧化物半导体场效应管(MOSFETs)等比缩小到45 nm技术节点,具有高介电常数的栅介质材料(高k材料)取代传统的SiO₂已经成为必然,然而Hf基高k材料在实际应用中仍然存在许多不足,而稀土元素掺杂在提高Hf基栅介质材料的k值、降低缺陷密度、调整MOSFETs器件的阈值电压等方面表现出明显的优势.本文综述了Hf基高k材料的发展历程,面临的挑战,稀土掺杂对Hf基高k材料性能的调节以及未来研究的趋势. 关键词： k栅介质')" href="#">Hf基高k栅介质 稀土掺杂 氧空位缺陷 有效功函数     

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain(LDD) overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.     

Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

The hysteresis effect in the output characteristics, originating from the floating body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs at different back-gate biases. I_D hysteresis has been developed to clarify the hysteresis characteristics. The fabricated devices show the positive and negative peaks in the I_D hysteresis. The experimental results show that the I_D hysteresis is sensitive to the back gate bias in 0.13-μm PD SOI MOSFETs and does not vary monotonously with the back-gate bias. Based on the steady-state Shockley--Read--Hall (SRH) recombination theory, we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.