A simple and accurate method to measure program/erase speed in a memory capacitor structure

With the merits of simple process and short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this time constant is greatly reduced and the measured minority carrier related program/erase speed is in agreement with the reported value in a transistor structure.     

Improved charge trapping flash device with Al2O3/HfSiO stack as blocking layer

In this paper, we investigate an Al₂O₃/HfSiO stack as the blocking layer of a metal-oxide-nitride-oxide-silicon-type (MONOS) memory capacitor. Compared with a memory capacitor with a single HfSiO layer as the blocking layer or an Al₂O₃/HfO₂ stack as the blocking layer, the sample with the Al₂O₃/HfSiO stack as the blocking layer shows high program/erase (P/E) speed and good data retention characteristics. These improved performances can be explained by energy band engineering. The experimental results demonstrate that the memory device with an Al₂O₃/HfSiO stack as the blocking layer has great potential for further high-performance nonvolatile memory applications.     

Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10¹⁸ cm^-3 and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.     

退火工艺对LaTiON和HfLaON存储层金属-氧化物-氮化物-氧化物-硅存储器特性的影响

采用反应溅射法, 分别制备以LaTiON, HfLaON为存储层的 金属-氧化物-氮化物-氧化物-硅 电容存储器, 研究了淀积后退火气氛(N₂, NH₃)对其存储性能的影响. 分析测试表明, 退火前LaTiON样品比HfLaON 样品具有更好的电荷保持特性, 但后者具有更大的存储窗口 (编程/擦除电压为+/-12 V时4.8 V); 对于退火样品, 由于NH₃的氮化作用, NH₃退火样品比N₂退火样品表现出更快的编程/擦除速度、更好的电荷保持特性和疲劳特性. 当编程/擦除电压为+/-12 V时, NH₃退火HfLaON样品的存储窗口为3.8 V, 且比NH₃退火LaTiON样品具有更好的电荷保持特性和疲劳特性.     

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal(Si-NC) nonvolatile memory(NVM) devices for its scaling down limit.In this work,we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor(CMOS) technology.It is found that the memory windows of eight kinds of test key cells are almost the same of about1.64 V @ ±7 V/1 ms,which are independent of the gate area,but mainly determined by the average size(12 nm) and areal density(1.8×10~(11)/cm~2) of Si-NCs.The program/erase(P/E) speed characteristics are almost independent of gate widths and lengths.However,the erase speed is faster than the program speed of test key cells,which is due to the different charging behaviors between electrons and holes during the operation processes.Furthermore,the data retention characteristic is also independent of the gate area.Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.     

Performance improvement of charge trap flash memory by using a composition-modulated high-k trapping layer

A composition-modulated （HfO2）x（Al2O3）1-x charge trapping layer is proposed for charge trap flash memory by controlling the A1 atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated （HfO2）x（Al2O3）l-x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application.     

Analysis of the mechanisms of electron recombination in HgCdTe infrared photodiode

This paper presents an experimental study of minority carrier lifetime and recombination mechanisms in HgCdTe photodiode. The excitation light source is a wavelength-tunable pulsed infrared laser. A constant background illumination has been introduced to minimize the effect of the junction equivalent capacitor and resistance. The decay of the photo-generated voltage is recorded by a storage oscilloscope. By fitting the exponentially decay curve, the time constant has been obtained which is regarded as the photo-generated minority carrier lifetime of the HgCdTe photodiode. The experimental results show that the carrier lifetime is in the range of 18–407 ns at 77 K for the measured detectors of four Cd compositions. It was found that the Auger recombination process is more effective for low Cd composition while the radiative recombination process became more important for high composition materials. The Shockley–Read–Hall recombination processes could not be ignored for all Cd composition.     

Improved characteristics for MOHOS memory with oxygen-rich GdO as charge storage layer annealed by NH3

Characteristics of metal–oxide–high-k–oxide–silicon (MOHOS) memories with oxygen-rich or oxygen-deficient GdO as charge storage layer annealed by NH₃ or N₂ are investigated. Transmission electron microscopy, X-ray photoelectron spectroscopy and X-ray diffraction are used to analyze the cross-sectional quality, composition and crystallinity, respectively, of the stacked gate dielectric with a structure of Al/Al₂O₃/GdO/SiO₂/Si. The MOHOS capacitor with oxygen-rich GdO annealed in NH₃ exhibits a good trade-off among its memory properties: large memory window (4.8 V at ±12 V, 1 s), high programming speed (2.6 V at ±12 V/100 μs), good endurance and retention properties (window degradation of 5 % after 10⁵ program/erase cycles and charge loss of 18.6 % at 85 °C after 10 years, respectively) due to passivation of oxygen vacancies, generation of deep-level traps in the grain boundaries of the GdO layer and suppression of the interlayer between GdO and SiO₂ by the NH₃ annealing.     

Charge storage characteristics in Al/AlN/Si metal–insulator–semiconductor structure based on deep traps in AlN layer

Charge storage characteristics in an Al/AlN/p-Si metal–insulator–semiconductor (MIS) structure have been investigated by capacitance–voltage and long-term capacitance measurements. Good program/erase behavior is observed in the AlN/Si structure, which is attributed to the trapping and detrapping of charges in deep traps of the AlN layer. In the long-term retention mode, a clear memory window is found 2000 s after removing a program/erase voltage of ±3 V, indicating good charge retention capability of the MIS structure. Further investigation shows that for a program pulse width of 500 ms, the charge storage does not occur when the pulse amplitude is smaller than a threshold value of ∼1 V. The trapped charge density increases linearly with increase of the pulse amplitude (>1 V) and tends to saturate at 2.5 V. With increasing program pulse width, the trapped charged density increases a little more than logarithmically. PACS 73.40.Kp; 72.20.Jv; 71.55.Eq     

LaON/SiO2和HfON/SiO2双隧穿层MONOS存储器存储特性的比较

本文对比研究了LaON/SiO₂和HfON/SiO₂双隧穿层MONOS存储器的存储特性. 实验结果表明,LaON/SiO₂双隧穿层MONOS存储器具有较大的存储窗口,快的编程/擦除速度及好的疲劳和保持特性. 其机理在于LaON较大的介电常数有效提高了编程/擦除过程中载流子的注入效率,较小的O 扩散系数减少了界面陷阱,从而减少了保持期间存储电荷通过陷阱辅助隧穿的泄漏. 而且N的结合在界面附近形成了强的La-N,Hf-N 和O-N键,可有效降低编程/擦除循环应力对界面的损伤,使器件具有好的疲劳特性. 此外,研究了退火温度对存储特性的影响,结果表明800 ℃退火样品的存储特性比700 ℃退火的好,这是因为800 ℃时NO退火可在LaON（HfON）中引入更多的N,且能更好释放应力,使介质中缺陷减少. 关键词： MONOS 双隧穿层 LaON HfON     

Channel length effect in a MOSFET structure by scanning capacitance microscopy

Depth dependent carrier density and trapped charges in a metal-oxide-semiconductor field effect transistor (MOSFET) like structure have been studied using scanning capacitance microscopy (SCM). For a MOSFET structure, since minority carrier can be provided by the source and drain diffusions, its response time is shorter than that of metal-oxide-semiconductor (MOS) system. So the high frequency C-V relation is slightly different from that of MOS capacitor and shows the characteristics dependent on the channel length. Bias dependent SCM images which represent the depth dependent carrier density and detrapping time constant of trapped charges in the oxide layer were observed to see the channel effect in a MOSFET structure.     

Memory characteristics and tunneling mechanism of Pt nano-crystals embedded in HfAlOx films for nonvolatile flash memory devices

A non-volatile flash memory device based on metal oxide semiconductor (MOS) capacitor structure has been fabricated using platinum nano-crystals(Pt–NCs) as storage units embedded in HfAlO_x high-k tunneling layers. Its memory characteristics and tunneling mechanism are characterized by capacitance–voltage(C–V) and flat-band voltage-time(ΔV_FB-T) measurements. A 6.5 V flat-band voltage (memory window) corresponding to the stored charge density of 2.29 × 10¹³ cm⁻² and about 88% stored electron reserved after apply ±8 V program or erase voltage for 10⁵ s at high frequency of 1 MHz was demonstrated. Investigation of leakage current–voltage(J–V) indicated that defects-enhanced Pool-Frenkel tunneling plays an important role in the tunneling mechanism for the storage charges. Hence, the Pt–NCs and HfAlO_x based MOS structure has a promising application in non-volatile flash memory devices.     

Comparison between N_2 and O_2 anneals on the integrity of an Al_2O_3/Si_3N_4/SiO_2/Si memory gate stack

In this paper the endurance characteristics and trap generation are investigated to study the effects of different postdeposition anneals(PDAs) on the integrity of an Al2O3/Si3N4/SiO2/Si memory gate stack. The flat-band voltage(Vfb)turnarounds are observed in both the programmed and erased states of the N2-PDA device. In contrast, this turnaround is observed only in the erased state of the O2-PDA device. The Vfbin the programmed state of the O2-PDA device keeps increasing with increasing program/erase(P/E) cycles. Through the analyses of endurance characteristics and the low voltage round-trip current transients, it is concluded that in both kinds of device there are an unknown type of pre-existing characteristic deep traps and P/E stress-induced positive oxide charges. In the O2-PDA device two extra types of trap are also found: the pre-existing border traps and the P/E stress-induced negative traps. Based on these four types of defects we can explain the endurance characteristics of two kinds of device. The switching property of pre-existing characteristic deep traps is also discussed.     

Formation and relaxation mechanisms of the self-polarization in thin ferroelectric films

The nature and mechanisms of formation of the spontaneous polarization arising in thin ferroelectric films in the course of formation of a thin-film capacitor structure and relaxation of this polarization under the action of an electric field, temperature, and illumination are discussed.     

铁电液晶光寻址空间光调制器性能分析

针对氢化非晶硅/铝/铁电液晶结构的光寻址空间光调制器（OASLM）,依据其等效电路模型,利用Pspice和Matlab软件对其分辨率、响应速度、对比度及灰度响应等性能进行了分析。结果表明:在铁电液晶（FLC）层厚度一定的情况下,减小光敏感层（a-Si:H层）的厚度可以提高FLC-OASLM的调制传递函数,从而提高分辨率;在其他参量一定的情况下,FLC-OASLM的响应速度随写入光光强增大而增大（写入光从0.08 mW/cm2增大到10 mW/cm2,延迟时间减小110 s,上升时间减小154 s）,随擦除光光强增大而减小（擦除光从0增大到1 mW/cm2,延迟时间增大41 s,上升时间仅增加3 s）;FLC-OASLM的对比度随控制光光强增大而增大,最终趋于一个稳定值21∶1;在其他参量不变时,随着擦除光光强的增大,输出光响应呈现等级下降,且发现当擦除光光强达到一定值（3 mW/cm2）后,擦除光的改变主要影响下降时间而对上升时间几乎无影响;合理设计激励源信号波形,可以得到超过十级灰度输出,表明擦除光具有实现FLC OASLM的灰度响应的功能。     

Engineering of tunnel barrier for highly integrated nonvolatile memory applications

In this paper, the engineered tunnel barrier technology is introduced by using the engineered tunnel barrier of VARIOT type (SiO₂/Si₃N₄/SiO₂) and CRESTED type (Si₃N₄/SiO₂/Si₃N₄) with Si₃N₄ and high-k HfO₂ layers as charge trapping layers, respectively. In addition, the high-k stacked VARIOT type of SiO₂/HfO₂/Al₂O₃ and Al₂O₃/HfO₂/Al₂O₃ are compared with O/N/O tunnel barrier memory. As a result, the engineered tunnel barrier memory device showed excellent memory characteristics compared to the single SiO₂ tunnel barrier memory device, such as very high P/E (program/erase) speed, good retention time and no degradation in endurance characteristics.     

LaTiON/LaON as band-engineered charge-trapping layer for nonvolatile memory applications

Charge-trapping characteristics of stacked LaTiON/LaON film were investigated based on Al/Al₂O₃/LaTiON-LaON/SiO₂/Si (band-engineered MONOS) capacitors. The physical properties of the high-k films were analyzed by X-ray diffraction, transmission electron microscopy and X-ray photoelectron spectroscopy. The band profile of this band-engineered MONOS device was characterized by investigating the current-conduction mechanism. By adopting stacked LaTiON/LaON film instead of LaON film as charge-trapping layer, improved electrical properties can be achieved in terms of larger memory window (5.4 V at ±10-V sweeping voltage), higher program speed with lower operating gate voltage (2.1 V at 100-μs +6 V), and smaller charge loss rate at 125 °C, mainly due to the variable tunneling path of charge carriers under program/erase and retention modes (realized by the band-engineered charge-trapping layer), high trap density of LaTiON, and large barrier height at LaTiON/SiO₂ (2.3 eV).     

A polarization-sensitive,self-powered,broadband and fast Ti3C2Tx MXene photodetector from visible to near-infrared driven by photogalvanic effects

Broadband, self-power, and polarization-sensitivity are desirable qualities for a photodetector. However, currently few photodetectors can fulfill these requirements simultaneously. Here, we propose a Ti₃C₂T_x (MXene) photodetector that is driven by the photogalvanic effect with impressive performances. A polarization-sensitive photocurrent is generated at zero bias under the illumination of linearly polarized laser light of 1064 nm, with an extinction ratio of 1.11. Meanwhile, a fast response with a 32/28 ms rise/decay time and a large on/off switching ratio of 120 are achieved. Besides, a robust zero-bias photocurrent is also generated in the photodetector under the illumination of 940 and 620 nm light, as well as the white light, showing a broadband photoresponse from the near-infrared to visible. Moreover, quantum transport simulations indicate that the photogalvanic effect plays an important role in the generation of the polarized photocurrent at zero bias due to the broken space inversion symmetry of the stacked few-layer Ti₃C₂T_x. Our results shed light on a potential application of the Ti₃C₂T_x–MXene in the low-power photodetection with high performances.     

Highly improved resistive switching performances of the self-doped Pt/HfO2:Cu/Cu devices by atomic layer deposition

Metal-oxide electrochemical metallization (ECM) memory is a promising candidate for the next generation nonvolatile memory. But this memory suffers from large dispersion of resistive switching parameters due to the intrinsic randomness of the conductive filament. In this work, we have proposed a self-doping approach to improve the resistive switching characteristics. The fabricated Pt/HfO₂:Cu/Cu device shows outstanding nonvolatile memory properties, including high uniformity, good endurance, long retention and fast switching speed. The results demonstrate that the self-doping approach is an effective method to improve the metal-oxide ECM memory performances and the self-doped Pt/HfO₂:Cu/Cu device has high potentiality for the nonvolatile memory applications in the future.     

MEMORY EFFECT AND CRYSTALLINE STRUCTURE IN POLYAMIDE 11

The memory effect in PA11 films is studied in close relation with the crystalline structure. In polyamide 11, [(CH₂)₁₀–CO–NH] _n , the polarity of the amide group induces hydrogen bonds between chains that are crucial to the crystalline structure and are responsible for the memory effect. During the forming from the melt, the polyamides are sheared, which leads to persistent chain alignments due to hydrogen bonds. In the present work, the crystalline structure of PA11 films has been studied by differential scanning calorimetry and wide angle x-ray scattering. The crystalline structure at room temperature depends on the cooling rate. A quench leads to the smectic δ′ structure, whereas a slow cooling favors the formation of the triclinic α phase in addition to the smectic δ′ phase. This study also shows the influence of an annealing in the melt on the crystalline structure. With increasing annealing time in the melt, the δ phase develops and the δ′ phase progressively vanishes. It seems necessary to maintain PA11 above the melting point for a long time to totally erase the structural evidence of the memory effect.