新型双异质结高电子迁移率晶体管的电流崩塌效应研究

针对传统单结GaN基高电子迁移率晶体管器件性能受电流崩塌效应和自加热效应限制的困境,对新型A1GaN/GaN/InGaN/GaN双异质结高电子迁移率晶体管的直流性质展开了系统研究.采用基于热电子效应和自加热效应的流体动力模型,研究了器件在不同偏压下电流崩塌和负微分电导效应与GaN沟道层厚度的相关.研究发现具有高势垒双异质的沟道层能更好地将电子限制在沟道中,显著减小高电场下热电子从沟道层向GaN缓冲层的穿透能力.提高GaN沟道层厚度可以有效抑制电流崩塌和和负微分输出电导,进而提高器件在高场作用下的性能.所得结果为进一步优化双异质结高电子迁移率晶体管结构提供了新思路,可促进新型GaN高电子迁移率晶体管器件在高功率、高频和高温等无线通讯领域内的广泛应用.     

AIGaN／GaN高速电子迁移率晶体管器件电流坍塌效应与界面热阻和温度的研究

本文系统研究了A1GaN／GaN基高速电子迁移率晶体管器件界面热阻和工作温度对器件在高功率下的电流坍塌效应的影响规律．研究发现低漏极电压下热电子是导致负微分输出电导的重要因素,器件工作温度变高会使负微分输出电导减小．高漏极电压下自加热效应是导致电流坍塌的一个重要因素．随着界面热阻的增加,器件跨导降低,阂值电压增大．同时,由于工作环境温度的增高,器件随之温度增高,载流子迁移率会显著降低．最终这两种因素会引起A1GaN／GaN基高速电子迁移率晶体管器件显著的电流坍塌效应,从而降低了器件整体性能．     

高功率微波作用下高电子迁移率晶体管的损伤机理

本文针对高电子迁移率晶体管在高功率微波注入条件下的损伤过程和机理进行了研究,借助SentaurusTCAD仿真软件建立了晶体管的二维电热模型,并仿真了高功率微波注入下的器件响应.探索了器件内部电流密度、电场强度、温度分布以及端电流随微波作用时间的变化规律.研究结果表明,当幅值为20 V,频率为14.9 GHz的微波信号由栅极注入后,器件正半周电流密度远大于负半周电流密度,而负半周电场强度高于正半周电场.在强电场和大电流的共同作用下,器件内部的升温过程同时发生在信号的正、负半周内.又因栅极下靠近源极侧既是电场最强处,也是电流最密集之处,使得温度峰值出现在该处.最后,对微波信号损伤的高电子迁移率晶体管进行表面形貌失效分析,表明仿真与实验结果符合良好.     

AlGaN/GaN 高速电子迁移率晶体管器件电流坍塌效应与界面热阻和温度的研究

本文系统研究了AlGaN/GaN基高速电子迁移率晶体管器件界面热阻和工作温度对器件在高功率下的电流坍塌效应的影响规律.研究发现低漏极电压下热电子是导致负微分输出电导的重要因素,器件工作温度变高会使负微分输出电导减小.高漏极电压下自加热效应是导致电流坍塌的一个重要因素.随着界面热阻的增加,器件跨导降低,阈值电压增大.同时,由于工作环境温度的增高,器件随之温度增高,载流子迁移率会显著降低. 最终这两种因素会引起AlGaN/GaN基高速电子迁移率晶体管器件显著的电流坍塌效应,从而降低了器件整体性能. 关键词： AlGaN/GaN HEMT 器件 热电子效应 自加热效应 电流坍塌效应     

高电子迁移率晶体管及其应用

简要介绍了高电子迁移率晶体管的基本原理，应用及近年来的进展，它具有的高速，高频，低噪声等优异性能，使它将成为未来的主流微波器件。     

氮化镓基高电子迁移率晶体管单粒子和总剂量效应的实验研究

利用重离子加速器和~(60)Co γ射线实验装置,开展了p型栅和共栅共源级联结构增强型氮化镓基高电子迁移率晶体管的单粒子效应和总剂量效应实验研究,给出了氮化镓器件单粒子效应安全工作区域、总剂量效应敏感参数以及辐射响应规律.实验发现, p型栅结构氮化镓器件具有较好的抗单粒子和总剂量辐射能力,其单粒子烧毁阈值大于37 MeV·cm~2/mg,抗总剂量效应水平高于1 Mrad (Si),而共栅共源级联结构氮化镓器件则对单粒子和总剂量辐照均很敏感,在线性能量传输值为22 MeV·cm~2/mg的重离子和累积总剂量为200 krad (Si)辐照时,器件的性能和功能出现异常.利用金相显微镜成像技术和聚焦离子束扫描技术分析氮化镓器件内部电路结构,揭示了共栅共源级联结构氮化镓器件发生单粒子烧毁现象和对总剂量效应敏感的原因.结果表明,单粒子效应诱发内部耗尽型氮化镓器件的栅肖特基势垒发生电子隧穿可能是共栅共源级联结构氮化镓器件发生源漏大电流的内在机制.同时发现,金属氧化物半导体场效应晶体管是导致共栅共源级联结构氮化镓器件对总剂量效应敏感的可能原因.     

GaN基HEMT器件的缺陷研究综述

GaN基高电子迁移率晶体管(HEMT)因具有高输出功率密度、高工作频率、高工作温度等优良特性,在高频大功率等领域具有广泛应用前景。目前,HEMT器件在材料生长和工艺制备方面都取得了巨大的进步。但是,由缺陷产生的陷阱效应一直是限制其发展的重要原因。本文首先论述了HEMT器件中的表面态、界面缺陷和体缺陷所在位置及其产生的原因。然后,阐述了由陷阱效应引起的器件电流崩塌、栅延迟、漏延迟、Kink效应等现象,从器件结构设计和工艺设计角度,总结提出了改善缺陷相关问题的主要措施,其中着重总结了器件盖帽层、表面处理、钝化层和场板结构4个方面的最新研究进展。最后,探索了GaN基HEMT器件在缺陷相关问题上的未来优化方向。     

AlGaN/GaN高电子迁移率晶体管肖特基高温退火机理研究

在不同应力条件下,研究了AlGaN/GaN高电子迁移率晶体管高温退火前后的电流崩塌、栅泄漏电流以及击穿电压的变化.结果表明,AlGaN/GaN高电子迁移率晶体管通过肖特基高温退火以后,器件的特性得到很大的改善.利用电镜扫描(SEM)和X射线光电子能谱(XPS)对高温退火前、后的肖特基接触界面进行深入分析,发现器件经过高温退火后,Ni和AlGaN层之间介质的去除,并且AlGaN材料表面附近的陷阱减少,使得肖特基有效势垒提高,从而提高器件的电学特性. 关键词： AlGaN/GaN高电子迁移率晶体管 肖特基接触 界面陷阱     

半导体量子电子和光电子器件

本文阐述了半导体异质结构电子的量子特性 ,如电子波输运、库仑阻塞效应等。介绍了几种新颖、典型的量子电子器件和量子光电子器件的物理模型和基本原理。这些器件包括了单电子晶体管、共振隧穿二极管、高电子迁移率晶体管、δ掺杂场效应晶体管、量子点元胞自动机、量子阱红外探测器、埋沟异质结半导体激光器、量子级联激光器等。给出了作者在半导体量子器件物理方面的最新研究结果。     

半导体量子电子和光电子器件

本阐述了半导体异质结构电子的量子特性,如电子波输运,库仑阻塞效应等,介绍了几种新颖,典型的量子电子器件和量子光电子器件的物理模型和基本原理,这些器件包括了单电子晶体管,共振隧穿二极管,高电子迁移率晶体管,δ掺杂场效应晶体管,量子点元胞自动机,量子阱红外探测器,埋沟异质结半导体激光器,量子级联激光器等,给出了作在半导体量子器件物理方面的最新研究结果。     

C band microwave damage characteristics of pseudomorphic high electron mobility transistor

The damage effect characteristics of Ga As pseudomorphic high electron mobility transistor(p HEMT) under the irradiation of C band high-power microwave(HPM) is investigated in this paper. Based on the theoretical analysis, the thermoelectric coupling model is established, and the key damage parameters of the device under typical pulse conditions are predicted, including the damage location, damage power, etc. By the injection effect test and device microanatomy analysis through using scanning electron microscope(SEM) and energy dispersive spectrometer(EDS), it is concluded that the gate metal in the first stage of the device is the vulnerable to HPM damage, especially the side below the gate near the source. The damage power in the injection test is about 40 d Bm and in good agreement with the simulation result. This work has a certain reference value for microwave damage assessment of p HEMT.     

Exploring the warped bulk

In this study, a gallium nitride (GaN) high electron mobility transistor (HEMT) with recessed insulator and barrier is reported. In the proposed structure, insulator is recessed into the barrier at the drain side and barrier is recessed into the buffer layer at the source side. We study important device characteristics such as electric field, breakdown voltage, drain current, maximum output power density, gate-drain capacitance, short channel effects and DC transconductance using two-dimensional and two-carrier device simulator. Recessed insulator in the drain side of the proposed structure reduces maximum electric field in the channel and therefore increases the breakdown voltage and maximum output power density compared to the conventional counterpart. Also, gate-drain capacitance value in the proposed structure is less than that of the conventional structure. Overall, the proposed structure reduces short channel effects. Because of the recessed regions at both the source and the drain sides, the average barrier thickness of the proposed structure is not changed. Thus, the drain current of the proposed structure is almost equivalent to that of the conventional transistor. In this work, length (L _r) and thickness (T _r) of the recessed region of the barrier at the source side are the same as those of the insulator at the drain side.     

Performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors

We report on the performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors （MOSHEMTs） and InA1N/GaN high electron mobility transistors （HEMTs）. The MOSHEMT presents a maximum drain current of 961 mA/mm at Vgs = 4 V and a maximum transconductance of 130 mS/mm compared with 710 mA/mm at Vgs = 1 V and 131 mS/mm for the HEMT device, while the gate leakage current in the reverse direction could be reduced by four orders of magnitude. Compared with the HEMT device of a similar geometry, MOSHEMT presents a large gate voltage swing and negligible current collapse.     

Optimization of field-plate AlGaN/GaN HFETs for high-voltage and high-frequency operation

We performed physics-based 2-dimensional TCAD device simulations to optimize field-plated AlGaN/GaN heterostructure field effect transistors (HFETs) for high-power and high-frequency operation. The effects of the field plate dimensions and the passivation dielectric materials were investigated. The results showed that dimensional changes in the field plates significantly affected the breakdown and frequency performance. Silicon nitride, a widely-used passivation material for this technology, also turned out to have a benign effect on high-voltage operation whereas it had a detrimental effect on high-frequency operation. In this work, double-layered passivation with a source field plate was proposed and optimized to secure both high-voltage and high-frequency operation. The optimized devices maintained high breakdown voltage performance without compromising frequency response and without increasing fabrication complexity.

     

不同晶面的氢终端单晶金刚石场效应晶体管特性

通过微波等离子体化学气相淀积技术生长单晶金刚石并切割得到(110)和(111)晶面金刚石片,以同批器件工艺制备两种晶面上栅长为6μm的氢终端单晶金刚石场效应管,从材料和器件特性两方面对两种晶面金刚石进行对比分析.(110)面和(111)面金刚石的表面形貌在氢终端处理后显著不同,光学性质则彼此相似.VGS=–4 V时,(111)金刚石器件获得的最大饱和电流为80.41 m A/mm,约为(110)金刚石器件的1.4倍;其导通电阻为48.51 W·mm,只有(110)金刚石器件导通电阻的67%.通过对器件电容-电压特性曲线的分析得到,(111)金刚石器件沟道中最大载流子密度与(110)金刚石器件差异不大.分析认为,(111)金刚石器件获得更高饱和电流和更低导通电阻,应归因于较低的方阻.     

Electronic transport properties of silicon junctionless nanowire transistors fabricated by femtosecond laser direct writing

Silicon junctionless nanowire transistor(JNT) is fabricated by femtosecond laser direct writing on a heavily n-doped SOI substrate.The performances of the transistor,i.e.,current drive,threshold voltage,subthreshold swing(SS),and electron mobility are evaluated.The device shows good gate control ability and low-temperature instability in a temperature range from 10 K to 300 K.The drain currents increasing by steps with the gate voltage are clearly observed from 10 K to50 K,which is attributed to the electron transport through one-dimensional(1D) subbands formed in the nanowire.Besides,the device exhibits a better low-field electron mobility of 290 cm~2·V~(-1)·s~(-1),implying that the silicon nanowires fabricated by femtosecond laser have good electrical properties.This approach provides a potential application for nanoscale device patterning.     

GaN基发光二极管衬底材料的研究进展

GaN基发光二极管(LED)作为第三代照明器件在近年来发展迅猛.衬底材料作为LED制造的基础,对器件制备与应用具有极其重要的影响.本文分析综述了衬底材料影响LED器件设计与制造的关键特性(晶格结构、热胀系数、热导率、光学透过率、导电性),对比了几种常见衬底材料(蓝宝石、碳化硅、单晶硅、氮化镓、氧化镓)在高质量外延层生长、高性能器件设计和衬底材料制备方面的研究进展,并对几种材料的发展前景做出了展望.     

Steady-state and transient electron transport within bulk wurtzite zinc oxide

We study the steady-state and transient electron transport that occurs within bulk wurtzite zinc oxide using an ensemble semi-classical three-valley Monte Carlo simulation approach. We find that for electric field strengths in excess of 180 kV/cm, the steady-state electron drift velocity associated with bulk wurtzite zinc oxide exceeds that associated with bulk wurtzite gallium nitride. We also present evidence to suggest that the negative differential mobility exhibited by the velocity-field characteristic associated with bulk wurtzite zinc oxide is not related to transitions to the upper valleys. The transient electron transport that occurs within bulk wurtzite zinc oxide is studied by examining how electrons, initially in thermal equilibrium, respond to the sudden application of a constant electric field. From these transient electron transport results, we conclude that for devices with dimensions smaller than 0.1 μm, gallium nitride based devices will offer the advantage, owing to their superior transient electron transport, while for devices with dimensions greater than 0.1 μm, zinc oxide based devices will offer the advantage, owing to their superior high-field steady-state electron transport.     

Thermal expansion imaging and finite element simulation of hot lines in high power AlGaN HEMT devices

The temperature and thermo-elastic expansion of the heated area in a high power, high electron mobility transistor (HEMT) device have been investigated by means of finite element calculations and scanning thermal expansion microscopy. With both procedures a hot line is located near the gate line of the transistor. To determine the absolute temperature, the thermo-elastic response was calibrated on the basis of the force–distance curve of the AFM and the thermal expansion of the gold layer on top of the heated areas. The maximum temperatures deduced by the two procedures are in reasonable agreement whereas discrepancies are found for the temperature profile of the hot line, pointing towards a possible influence of the large aspect ratio of the device on the thermo-elastic measurement.