考虑通孔和边缘效应的互连网络热电分析

考虑互连通孔和边缘效应,建立互连层间、层内、通孔热阻模型,利用热电二元性,提出一种考虑温度效应对热流影响的热电耦合仿真方法,利用热电之间的反馈关系,修正建模后的温度分布对节点网络热流的影响.并对以聚合物和硅氧化物为介质的多层互连进行分析,以有限元建模结果为参照,与已有模型相比,互连热分布结果的相对标准差分别降低了71.2%、12.9%.考虑通孔效应和边缘效应后,该方法在不同纳米级工艺中所得峰值温升,较已有模型均有一定程度的降低.     

一种考虑温度的分布式互连线功耗模型

基于集总式电阻-电容树形功耗模型,考虑了非均匀温度分布对互连线电阻的影响,提出了一种新的分布式互连线动态功耗解析模型,解决了集总式模型不能表征非均匀温度变化带来的电阻变化的问题,并计算了一次非理想的激励冲激下整个互连模型消耗的总能量.基于所提出的分布式互连线功耗模型,计算了纳米级互补金属氧化物半导体（CMOS）工艺典型长度互连线的Elmore延时和功耗,发现非均匀温度分布对互连功耗的影响随着互连线长度的增加而增加,单位长度功耗随着CMOS工艺特征尺寸的变化而基本不变.文中所提出的功耗模型可以用来精确估算互 关键词： 互连线 温度梯度 动态功耗模型 纳米级互补金属氧化物半导体     

考虑通孔横向热传输效应的三维集成电路热分析

考虑横向热传输效应,构造一种包含通孔结构的叠层芯片三维热传输模型.在具体的工艺参数下验证叠层芯片层数、通孔密度、通孔直径和后端线互连层厚度对三维集成电路热传输的影响.结果显示,采用该模型仿真得到的各层芯片温升要低于不考虑横向热传输时所得到的温升,差异最大可达10%以上,并且集成度要求越高,其横向热传输效应的影响越明显.该模型更符合实际情况,能够更准确地分析三维集成电路的各层芯片温度.     

一种基于延时和带宽约束的纳米级互连线优化模型

基于RLC互连线延时模型,通过缓冲器插入和改变互连线宽及线间距,提出了一种基于延时和带宽约束的互连功耗-缓冲器面积的乘积优化模型.基于90 nm,65 nm和45 nm CMOS工艺验证了互连线优化模型,在牺牲1/3和1/2的带宽的前提下,平均能够节省46%和61%的互连功耗,以及65%和83%的缓冲器面积,能应用于纳米级SOC的计算机辅助设计. 关键词： 纳米互连功耗 缓冲器面积 延时 带宽     

一种基于纳米级CMOS工艺的互连线串扰RLC解析模型

基于纳米级CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了分布式RLC耦合互连解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下提出了受扰线远端的数值表达式. 基于90和65 nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在4%内,能应用于纳米级片上系统（SOC）的电子设计自动化（EDA）设计和集成电路优化设计. 关键词： 纳米级CMOS 互连串扰 分布式 RLC解析模型')" href="#">RLC解析模型     

一种基于纳米级CMOS工艺的互连线串扰RLC解析模型

基于纳米级CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了分布式RLC耦合互连解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下提出了受扰线远端的数值表达式. 基于90和65 nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在4%内,能应用于纳米级片上系统(SOC)的电子设计自动化(EDA)设计和集成电路优化设计.     

有丢失物缺陷的铜互连线中位寿命的定量研究

本文研究了六层互连线上的丢失物缺陷对互连电迁移中位寿命的影响,提出了各层互连线缺陷处的温度模型和缺陷在不同互连层的中位寿命模型,能够定量地计算缺陷对互连电迁移中位寿命的影响,给出了提高互连线中位寿命的方法.研究结果表明：互连线宽度与缺陷处互连线有效宽度的比值越大,互连线寿命越短;缺陷处的温度越高,互连线寿命越短.在互连线参数变化明显的层与层之间,互连线寿命受比值和温度的双重影响,寿命急剧下降.根据该物理模型可以准确计算出互连线具体的温度和寿命数据,可以直接指导集成电路的设计和工艺制造. 关键词： 丢失物缺陷 中位寿命 可靠性 铜互连     

考虑非均匀温度分布效应的缓冲器插入最优尺寸研究

基于非均匀温度分布效应对互连延时的影响, 提出了一种求解互连非均匀温度分布情况下的缓冲器最优尺寸的模型. 给出了非均匀温度分布情况下的RC互连延时解析表达式, 通过引入温度效应消除因子, 得出了最优插入缓冲器尺寸以使互连总延时最优. 针对90 nm和65 nm工艺节点, 对所提模型进行了仿真验证, 结果显示, 相较于以往同类模型, 本文所提模型由于考虑了互连非均匀温度分布效应, 更加准确有效, 且在保证互连延时最优的情况下有效地提高了芯片面积的利用.     

CMOS电路低温特性及其仿真

本文采用0.25微米工艺制备了CMOS器件和电路,通过对300K、77K和4K温度下器件和电路特性的测量,研究了工作温度降低对CMOS电路特性的影响.通过讨论MOSFET器件和互连线主要特性参数随温度的变化情况,修改了常温CMOS BSIM3模型以及互连线参数,建立了77K、4K温度下的低温电路仿真模型.利用上述新建立的低温电路仿真模型对CMOS电路进行仿真,并将仿真结果与实际测量结果比较,获得了比较一致的结果.研究表明在4K温度下CMOS电路的工作性能大约有50%到60%的改善.     

基于RLCπ型等效模型的互连网络精确焦耳热功耗计算

基于互连网络的RLC π型等效模型,考虑电感的屏蔽作用和非理想的阶跃激励,提出了互连线网络在斜阶跃激励下的焦耳热功耗计算方法,极大地简化了互连网络中电流和功耗的表达式. 基于90 nm金属氧化物半导体(CMOS)工艺的互连参数对所提出的计算方法进行了计算和仿真验证,对于上升信号小于1 ns的情况,计算结果与Hspice仿真结果的误差小于3%,具有很高的精度,适合应用于大规模互连网络中的功耗估算和热分析.     

An RLC interconnect analyzable crosstalk model considering self-heating effect

According to the thermal profile of actual multilevel interconnects, in this paper we propose a temperature distribution model of multilevel interconnects and derive an analytical crosstalk model for the distributed resistance-inductance-capacitance (RLC) interconnect considering effect of thermal profile. According to the 65-nm complementary metal-oxide semiconductor (CMOS) process, we compare the proposed RLC analytical crosstalk model with the Hspice simulation results for different interconnect coupling conditions and the absolute error is within 6.5%. The computed results of the proposed analytical crosstalk model show that RCL crosstalk decreases with the increase of current density and increases with the increase of insulator thickness. This analytical crosstalk model can be applied to the electronic design automation (EDA) and the design optimization for nanometer CMOS integrated circuits.     

A novel analytical thermal model for multilevel nano-scale interconnects considering the via effect

Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65~nm complementary metal oxide semiconductor (CMOS) process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design (CAD) of very large-scale integrated circuits (VLSIs) in nano-scale technologies.     

A multilevel nano-scale interconnection RLC delay model

Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit,this paper proposes a multilevel nano-scale interconnection RLC delay model with the method of numerical analysis,the proposed analytical model has summed up the influence of the configuration of multilevel interconnections,the via heat transfer and self-heating effect on the interconnection delay,which is closer to the actual situation.Delay simulation results show that the proposed model has high precision within 5% errors for global interconnections based on the 65 nm CMOS interconnection and material parameter,which can be applied in nanometer CMOS system chip computer-aided design.     

Cryogenically Cooled CMOS

The factors affecting the feasibility of cryogenically cooled CMOS are reviewed. This approach becomes more attractive as CMOS feature sizes shrink below 250?nm where chip performance is limited by interconnect characteristics. The impact of interconnects is demonstrated using a methodology for estimating interconnect-limited CMOS performance. The cryogenic behavior of normal and superconducting interconnects is reviewed. Cooling the best normal interconnect metals such as Al or Cu to 77?K can produce 9×lower resistivity. High-temperature superconductors can produce lower resistance at GHz clock frequencies, but would be difficult to produce on low dielectric substrates compatible with silicon technology. Performance doubling has been demonstrated for CMOS circuits operating at liquid nitrogen temperature. Comparable performance improvements may be expected down to below 100?nm if process technology is adjusted appropriately. In addition, dramatic increases in DRAM storage times result from exponential decreases in subthreshold leakage currents. Circuit reliability should increase correspondingly, apart from hot-carrier induced degradation. Thermally efficient packages and refrigerators are required for cryogenic CMOS. Microchannel heat exchangers can produce thermally efficient cryogenic packages. However, thermodynamic limits to refrigerator performance may make operation at higher cryogenic temperatures more attractive.     

考虑自热效应的互连线功耗优化模型

基于互连线的分布式功耗模型,考虑自热效应的同时采用非均匀互连线结构,提出了一种基于延时、带宽、面积、最小线宽和最小线间距约束的互连动态功耗优化模型.分别在90和65 nm互补金属氧化物半导体工艺节点下验证了功耗优化模型的有效性,在工艺约束下同时不牺牲延时、带宽和面积所提模型能够降低高达35％互连线功耗.该模型适用于片上网络构架中大型互连路由结构和时钟网络优化设计.     

A novel low-swing interconnect optimization model with delay and bandwidth constraints

Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits.Based on the RLC interconnect delay model,by wire sizing,wire spacing and adopting low-swing interconnect technology,this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously.The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor(CMOS) interconnect parameters.The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process.The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.     

An interconnect width and spacing optimization model considering scattering effect

As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact of the scattering effect on latency and bandwidth, this paper first presents the quality-factor model which optimises latency and bandwidth effectively with the consideration of the scattering effect. Then we obtain the analytical model of line width and spacing with application of curve-fitting method. The proposed model has been verified and compared based on the nano-scale CMOS technology. This optimisation model algorithm is simple and can be applied to the interconnection system optimal design of nano-scale integrated circuits.