Snapback应力引起的90 nm NMOSFET's栅氧化层损伤研究

实验结果发现突发击穿(snapback)，偏置下雪崩热空穴注入NMOSFET栅氧化层，产生界面态，同时空穴会陷落在氧化层中.由于栅氧化层很薄，陷落的空穴会与隧穿入氧化层中的电子复合形成大量中性电子陷阱，使得栅隧穿电流不断增大.这些氧化层电子陷阱俘获电子后带负电，引起阈值电压增大、亚阈值电流减小.关态漏泄漏电流的退化分两个阶段：第一阶段亚阈值电流是主要成分，第二阶段栅电流是主要成分.在预加热电子(HE)应力后，HE产生的界面陷阱在snapback应力期间可以屏蔽雪崩热空穴注入栅氧化层，使器件snapback开态和关态特性退化变小. 关键词： 突发击穿 软击穿 应力引起的泄漏电流 热电子应力     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

Valence band electron tunneling in metal-oxide-silicon structures

Experimental results are presented for the substrate current appearing in thin oxide metal-oxide-silicon capacitors with a shallow n/p junction beneath the gate when a positive gate voltage in the tunneling regime is applied. The analysis of the current-voltage characteristics shows that for an oxide voltage drop lower than about 5 V the substrate current is due to electron tunneling from the silicon valence band. The dispersion relation in the energy range extending 3 eV below the oxide conduction band is determined from the voltage dependence of the current in the direct tunneling regime. An effective mass of about 0.8m_e is found near the edge of the oxide conduction band, while for lower energies a strong decrease of the effective mass is observed.     

A simplified post-soft-breakdown current model for MOS devices

Based on the tunneling current model, a simplified current model is developed for MOS devices after soft breakdown (SBD). The post-soft-breakdown current consists of modified direct tunneling current and Fowler Nordheim (FN) tunneling current. Considering the change of gate oxide after soft breakdown, impacts of soft breakdown on the dielectric constant, and effective electron mass of the gate oxide are discussed, and their values are obtained by fitting simulation results to experimental data. It is found that the effective electron mass is decreased after soft breakdown due to damaged oxide, while the dielectric constant is increased after soft breakdown due to interface distortion. In this way, the leakage current after soft breakdown can be accurately calculated. The validity of the proposed model is confirmed by experimental results. Z.L. Li currently is with the Department of Electrical and Electronic Engineering, University of Hong Kong.     

SILC during NBTI Stress in PMOSFETs with Ultra-Thin SiON Gate Dielectrics

Negative bias temperature instability （NBTI） and stress-induced leakage current （SILC） both are more serious due to the aggressive scaling lowering of devices. We investigate the SILC during NBTI stress in PMOSFETs with ultra-thin gate dielectrics. The SILC sensed range from -1 V to 1 V is divided into four parts： the on-state SILC, the near-zero SILC, the off-state SILC sensed at lower positive voltages and the one sensed at higher positive voltages. We develop a model of tunnelling assisted by interface states and oxide bulk traps to explain the four different parts of SILC during NBTI stress.     

应力导致的薄栅氧化层漏电流瞬态特性研究

分别研究了FN隧穿应力和热空穴(HH)应力导致的薄栅氧化层漏电流瞬态特性.在这两种应力条件下,应力导致的漏电流(SILC)与时间的关系均服从幂函数关系,但是二者的幂指数不同.热空穴应力导致的漏电流中,幂指数明显偏离-1,热空穴应力导致的漏电流具有更加显著的瞬态特性.研究结果表明:热空穴SILC机制是由于氧化层空穴的退陷阱效应和正电荷辅助遂穿中心的湮没.利用热电子注入技术,正电荷辅助隧穿电流可被大大地减弱.     

γ射线总剂量辐照对单轴应变Si纳米n型金属氧化物半导体场效应晶体管栅隧穿电流的影响

基于γ射线辐照条件下单轴应变Si纳米n型金属氧化物半导体场效应晶体管(NMOSFET)载流子的微观输运机制,揭示了单轴应变Si纳米NMOSFET器件电学特性随总剂量辐照的变化规律,同时基于量子机制建立了小尺寸单轴应变Si NMOSFET在γ射线辐照条件下的栅隧穿电流模型,应用Matlab对该模型进行了数值模拟仿真,探究了总剂量、器件几何结构参数、材料物理参数等对栅隧穿电流的影响.此外,通过实验进行对比,该模型仿真结果和总剂量辐照实验测试结果基本符合,从而验证了模型的可行性.本文所建模型为研究纳米级单轴应变Si NMOSFET应变集成器件可靠性及电路的应用提供了有价值的理论指导与实践基础.     

Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10¹⁸ cm^-3 and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.     

电离辐射对部分耗尽绝缘体上硅器件低频噪声特性的影响

本文针对辐射前后部分耗尽结构绝缘体上硅(SOI)器件的电学特性与低频噪声特性开展试验研究. 受辐射诱生埋氧化层固定电荷与界面态的影响, 当辐射总剂量达到1 M rad(Si) (1 rad = 10^-2 Gy)条件下, SOI器件背栅阈值电压从44.72 V 减小至12.88 V、表面电子有效迁移率从473.7 cm²/V·s降低至419.8 cm²/V· s、亚阈斜率从2.47 V/dec增加至3.93 V/dec; 基于辐射前后亚阈斜率及阈值电压的变化, 可提取得到辐射诱生界面态与氧化层固定电荷密度分别为5.33×10¹¹ cm^{- 2}与2.36×10¹² cm^-2. 受辐射在埋氧化层-硅界面处诱生边界陷阱、氧化层固定电荷与界面态的影响, 辐射后埋氧化层-硅界面处电子被陷阱俘获/释放的行为加剧, 造成SOI 器件背栅平带电压噪声功率谱密度由7×10^{- 10} V²·Hz^-1增加至1.8×10^-9 V² ·Hz^-1; 基于载流子数随机涨落模型可提取得到辐射前后SOI器件埋氧化层界面附近缺陷态密度之和约为1.42×10¹⁷ cm^-3·eV^-1和3.66×10¹⁷ cm^-3·eV^-1. 考虑隧穿削弱因子、隧穿距离与时间常数之间关系, 本文计算得到辐射前后埋氧化层内陷阱电荷密度随空间分布的变化.     

动态应力下超薄栅氧化层经时击穿的可靠性评价

实验发现动态电压应力条件下,由于栅氧化层很薄,高电平应力时间内隧穿入氧化层的电子与陷落在氧化层中的空穴复合产生中性电子陷阱,中性电子陷阱辅助电子隧穿.由于每个周期的高电平时间较短(远远低于电荷的复合时间),隧穿到氧化层的电子很少,同时低电平应力时间内一部分电荷退陷,形成的中性电子陷阱更少.随着应力时间的累积,中性电子陷阱达到某个临界值,栅氧化层突然击穿.高电平时形成的陷阱较少和低电平时一部分电荷退陷,使得器件的寿命提高. 关键词： 超薄栅氧化层 斜坡电压 经时击穿     

Degradation of Ultra-Thin Gate Oxide NMOSFETs under CVDT and SHE Stresses

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT)stresses are studied using NMOSFET with 1.4- nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown.     

Temperature-dependent current conduction mechanism and charge trapping in Ta2O5 RF-sputtered on GaN

A gallium nitride (GaN) based Metal-Oxide-Semiconductor (MOS) capacitor was fabricated using radio frequency (RF)-sputtered tantalum oxide (Ta₂O₅) as the high-k gate dielectric. Electrical characteristics of this capacitor were evaluated via capacitance–voltage (C–V), current–voltage (I–V), and interface trap density (D_it) measurements with emphasis on the substrate temperature dependence ranging from 25 °C to 200 °C. Charge trapping and conduction mechanism in Ta₂O₅ were investigated. The experimental results suggested that higher substrate temperature rendered higher oxide capacitance, reduced gate leakage current, and lowered mid-gap interface trap density at the expenses of high border traps and high fixed oxide charges. The gate leakage current through Ta₂O₅ was found to obey the Ohm's conduction at lower gate bias and the Poole–Frenkel conduction at higher gate bias.     

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and V_h degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.     

Influence of Si/SiO2 interface properties on electrical performance and breakdown characteristics of ultrathin stacked oxide/nitride dielectric films

In this work, the influence of Si/SiO₂ interface properties, interface nitridation and remote-plasma-assisted oxidation (RPAO) thickness (<1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxide/nitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/SiO₂ interface evidenced by less negative V_t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C-V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress.     

Numerical analysis of gate leakage current in AlGaN Schottky diodes

We studied theoretically the influence of the tunneling current on the leakage current in AlGaN Schottky diodes. It is shown that the most important conductance mechanism in these structures is the tunneling. The thermionic emission has lower influence on the total current practically throughout the whole reverse bias range and doping concentrations studied. For high doping concentrations we found very slow temperature dependence of the diode current.     

High temperature characteristics of AlGaN/GaN high electron mobility transistors

Direct current (DC) and pulsed measurements are performed to determine the degradation mechanisms of AlGaN/GaN high electron mobility transistors (HEMTs) under high temperature. The degradation of the DC characteristics is mainly attributed to the reduction in the density and the mobility of the two-dimensional electron gas (2DEG). The pulsed measurements indicate that the trap assisted tunneling is the dominant gate leakage mechanism in the temperature range of interest. The traps in the barrier layer become active as the temperature increases, which is conducive to the electron tunneling between the gate and the channel. The enhancement of the tunneling results in the weakening of the current collapse effects, as the electrons trapped by the barrier traps can escape more easily at the higher temperature.     

Application of superlattice gate and modulation-doped buffer for GaAs power MESFET grown by MBE

A new power GaAs MESFET (SGMBT), using the undoped superlattice gate and modulation-doped (MD) buffer, has been fabricated successfully by MBE. A much higher gate-drain breakdown voltage (30 V) and lower gate reverse leakage current have been obtained due to the existence of the undoped AlGaAs/GaAs superlattice gate insulator. The use of MD buffer structure introduces a high output resistance and low trap concentration at AlGaAs/GaAs interface. The degradation region at channel-buffer interface is estimated to be smaller than 40 Å. Thus the sharpness and smoothness between active channel and buffer is truly improved by the insertion of MD structure. The maximum output saturation current and output power of SGMBT are 300 mA/mm and 0.67 W/mm, respectively. By optimizing the device geometry and gate dimension, the output performance of SGMBT can be improved further.     

Mechanism of NBTI Recovery under Negative Voltage Stress

Recovery phenomenon is observed under negative gate voltage stress which is smaller than the previous degradation stress. We focus on the drain current to study the degradation and recovery of negative bias temperature instability (NBTI) with a real-time method. By this method, different recovery phenomena among different size devices are observed. Under negative recovery stress, the drain current gradually recovers for the large size devices and gets into recovery saturation when long recovery time is involved. For small-size devices, a step-like recovery of drain current is observed. The recovery of the drain current is mainly caused by the holes detrapping and tunnelling back to the channel surface which are trapped in oxide. The model of hole detrapping explains the recovery under negative voltage stress reasonably.     

Individual,attractive defect centers in the SiO2-Si interface of μm-sized MOSFETs

In a micron-sized p-channel MOSFET, the alternate capture and emission of holes into a Coulomb-attractive defect center is analyzed by the random telegraph signal in the source-drain current. Anomalous switching is observed with a high channel conductance when the defect center is occupied, and a low channel conductance after re-emission. The rate constants show an inverse symmetry for capture and emission. The measured results are interpreted by a tunneling transfer of a hole bound in the channel at the attractive center to the defect center 2.4 nm deep in the oxide and vice versa. The energy offset of the two stable configurations can be linearly varied by the gate voltage. An excited state 40 meV above the ground state is observed for the defect level. The anomalous switching is caused by a mobility change rather than by a change in mobile charge carrier density. The tunneling transfer for Coulomb-attractive centers differs from the transfer observed for Coulomb-repulsive centers where activated emission is reported.