阶梯氧化层新型折叠硅横向双扩散功率器件

为了设计功率集成电路所需的低功耗横向功率器件, 提出了一种具有阶梯氧化层折叠硅横向双扩散金属-氧化物-半导体(step oxide folding LDMOS, SOFLDMOS)新结构. 这种结构将阶梯氧化层覆盖在具有周期分布的折叠硅表面, 利用阶梯氧化层的电场调制效应, 通过在表面电场分布中引入新的电场峰而使表面电场分布均匀, 提高了器件的耐压范围, 解决了文献提出的折叠积累型横向双扩散金属-氧化物-半导体器件击穿电压受限的问题. 通过三维仿真软件ISE分析获得, SOFLDMOS 结构打破了硅的极限关系, 充分利用了电场调制效应、多数载流子积累和硅表面导电区倍增效应, 漏极饱和电流比一般LDMOS 提高3.4倍左右, 可以在62 V左右的反向击穿电压条件下, 获得0.74 mΩ·cm²超低的比导通电阻, 远低于传统LDMOS相同击穿电压下2.0 mΩ·cm²比导通电阻, 为实现低压功率集成电路对低功耗横向功率器件的要求提供了一种可选的方案.     

具有半绝缘多晶硅完全三维超结横向功率器件

为了突破传统LDMOS (lateral double-diffused MOSFET)器件击穿电压与比导通电阻的硅极限的2.5 次方关系, 降低LDMOS器件的功率损耗, 提高功率集成电路的功率驱动能力, 提出了一种具有半绝缘多晶硅SIPOS (semi-insulating poly silicon)覆盖的完全3 D-RESURF (three-dimensional reduced surface field)新型Super Junction-LDMOS结构(SIPOS SJ-LDMOS). 这种结构利用SIPOS的电场调制作用使SJ-LDMOS的表面电场分布均匀, 将器件单位长度的耐压量提高到19.4 V/μupm; 覆盖于漂移区表面的SIPOS使SJ-LDMOS沿三维方向均受到电场调制, 实现了LDMOS的完全3 D-RESURF效应, 使更高浓度的漂移区完全耗尽而达到高的击穿电压; 当器件开态工作时, 覆盖于薄场氧化层表面的SIPOS的电场作用使SJ-LDMOS的漂移区表面形成多数载流子积累, 器件比导通电阻降低. 利用器件仿真软件ISE分析获得, 当SIPOS SJ-LDMOS的击穿电压为388 V时, 比导通电阻为20.87 mΩ·cm², 相同结构参数条件下, N-buffer SJ-LDMOS的击穿电压为287 V, 比导通电阻为31.14 mΩ·cm²; 一般SJ-LDMOS 的击穿电压仅为180 V, 比导通电阻为71.82 mΩ·cm².     

具有L型源极场板的双槽绝缘体上硅高压器件新结构

为了提高小尺寸绝缘体上硅(SOI)器件的击穿电压,同时降低器件比导通电阻,提出了一种具有L型源极场板的双槽SOI高压器件新结构.该结构具有如下特征:首先,采用了槽栅结构,使电流纵向传导面积加宽,降低了器件的比导通电阻;其次,在漂移区引入了Si O2槽型介质层,该介质层的高电场使器件的击穿电压显著提高;第三,在槽型介质层中引入了L型源极场板,该场板调制了漂移区电场,使优化漂移区掺杂浓度大幅增加,降低了器件的比导通电阻.二维数值仿真结果表明:与传统SOI结构相比,在相同器件尺寸时,新结构的击穿电压提高了151%,比导通电阻降低了20%;在相同击穿电压时,比导通电阻降低了80%.与相同器件尺寸的双槽SOI结构相比,新结构保持了双槽SOI结构的高击穿电压特性,同时,比导通电阻降低了26%.     

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.     

双面阶梯埋氧层部分SOI高压器件新结构

提出了双面阶梯埋氧层部分绝缘硅(silicon on insulator,SIO)高压器件新结构. 双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布, 耗尽层通过源极下硅窗口进一步向硅衬底扩展, 使埋氧层中纵向电场高达常规SOI结构的两倍, 且缓解了常规SOI结构的自热效应. 建立了漂移区电场的二维解析模型, 获得了器件结构参数间的优化关系. 结果表明, 在导通电阻相近的情况下, 双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58％, 温度降低10—30K. 关键词： 双面阶梯 埋氧层 调制 自热效应     

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

新型缓冲层分区电场调制横向双扩散超结功率器件

为了突破传统横向双扩散金属-氧化物-半导体器件(lateral double-diffused MOSFET)击穿电压与比导通电阻的极限关系,本文在缓冲层横向双扩散超结功率器件(super junction LDMOS-SJ LDMOS)结构基础上,提出了具有缓冲层分区新型SJ-LDMOS结构.新结构利用电场调制效应将分区缓冲层产生的电场峰引入超结(super junction)表面而优化了SJ-LDMOS的表面电场分布,缓解了横向LDMOS器件由于受纵向电场影响使横向电场分布不均匀、横向单位耐压量低的问题.利用仿真分析软件ISE分析表明,优化条件下,当缓冲层分区为3时,提出的缓冲层分区SJ-LDMOS表面电场最优,击穿电压达到饱和时较一般LDMOS结构提高了50%左右,较缓冲层SJ-LDMOS结构提高了32%左右,横向单位耐压量达到18.48 V/μm.击穿电压为382 V的缓冲层分区SJ-LDMOS,比导通电阻为25.6 mΩ·cm2,突破了一般LDMOS击穿电压为254 V时比导通电阻为71.8 mΩ·cm2的极限关系.     

Modeling of 4H--SiC multi-floating-junction Schottky barrier diode

This paper develops a new and easy to implement analytical model for the specific on-resistance and electric field distribution along the critical path for 4H-SiC multi-floating junction Schottky barrier diode. Considering the charge compensation effects by the multilayer of buried opposite doped regions, it improves the breakdown voltage a lot in comparison with conventional one with the same on-resistance. The forward resistance of the floating junction Schottky barrier diode consists of several components and the electric field can be understood with superposition concept, both are consistent with MEDICI simulation results. Moreover, device parameters are optimized and the analyses show that in comparison with one layer floating junction, multilayer of floating junction layer is an effective way to increase the device performance when specific resistance and the breakdown voltage are traded off. The results show that the specific resistance increases 3.2 mΩ·cm 2 and breakdown voltage increases 422 V with an additional floating junction for the given structure.     

Control of electric field in 4H-SiC UMOSFET: Physical investigation

In this paper, we show how breakdown voltage (V_BR) and the specific on-resistance (R_on) can be improved simply by controlling of the electric field in a power 4H-SiC UMOSFET. The key idea in this work is increasing the uniformity of the electric field profile by inserting a region with a graded doping density (GD region) in the drift region. The doping density of inserted region is decreased gradually from top to bottom, called Graded Doping Region UMOSFET (GDR-UMOSFET). The GD region results in a more uniform electric field profile in comparison with a conventional UMOSFET (C-UMOSFET) and a UMOSFET with an accumulation layer (AL-UMOSFET). This in turn improves breakdown voltage. Using two-dimensional two-carrier simulation, we demonstrate that the GDR-UMOSFET shows higher breakdown voltage and lower specific on-resistance. Our results show the maximum breakdown voltage of 1340 V is obtained for the GDR-UMOSFET with 10 µm drift region length, while at the same drift region length and approximated doping density, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 V and 703 V, respectively.     

具有p-GaN岛状埋层耐压结构的横向AlGaN/GaN高电子迁移率晶体管

GaN基高电子迁移率晶体管(HEMT)相对较低的击穿电压严重限制了其大功率应用.为了进一步改善器件的击穿特性,通过在n-GaN外延缓冲层中引入六个等间距p-GaN岛掩埋缓冲层(PIBL)构成p-n结,提出一种基于p-GaN埋层结构的新型高耐压AlGaN/GaN HEMT器件结构.Sentaurus TCAD仿真结果表明,在关态高漏极电压状态下,p-GaN埋层引入的多个反向p-n结不仅能够有效调制PIBL AlGaN/GaN HEMT的表面电场和体电场分布,而且对于缓冲层泄漏电流有一定的抑制作用,这保证了栅漏间距为10μm的PIBL HEMT能够达到超过1700 V的高击穿电压(BV),是常规结构AlGaN/GaN HEMT击穿电压(580 V)的3倍.同时,PIBL结构AlGaN/GaN HEMT的特征导通电阻仅为1.47 m?·cm~2,因此获得了高达1966 MW·cm~(-2)的品质因数(FOM=BV~2/R_(on,sp)).相比于常规的AlGaN/GaN HEMT,基于新型p-GaN埋岛结构的HEMT器件在保持较低特征导通电阻的同时具有更高的击穿电压,这使得该结构在高功率电力电子器件领域具有很好的应用前景.     

Hybrid-anode structure designed for a high-performance quasi-vertical GaN Schottky barrier diode

A quasi-vertical GaN Schottky barrier diode with a hybrid anode structure is proposed to trade off the on-resistance and the breakdown voltage. By inserting a SiN dielectric between the anode metal with a relatively small length, it suppresses the electric field crowding effect without presenting an obvious effect on the forward characteristics. The enhanced breakdown voltage is ascribed to the charge-coupling effect between the insulation dielectric layer and GaN. On the other hand, the current density is decreased beneath the dielectric layer with the increasing length of the SiN, resulting in a high on-resistance. Furthermore, the introduction of the field plate on the side wall forms an metal-oxide-semiconductor (MOS) channel and decreases the series resistance, but also shows an obvious electric field crowding effect at the bottom of the mesa due to the quasi-vertical structure.     

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance (R on,sp ) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage V d is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field E I and the breakdown voltage (BV) of ABE SOI are 545 V/μm and -587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low R on,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results.     

A-188 V 7.2Ω·mm~2,P-channel high voltage device formed on an epitaxy-SIMOX substrate

This paper proposes a new n +-charge island (NCI) P-channel lateral double diffused metal-oxide semiconductor (LDMOS) based on silicon epitaxial separation by implantation oxygen (E-SIMOX) substrate.Higher concentration self-adapted holes resulting from a vertical electric field are located in the spacing of two neighbouring n +-regions on the interface of a buried oxide layer,and therefore the electric field of a dielectric buried layer (E I) is enhanced by these holes effectively,leading to an improved breakdown voltage (BV).The V B and E I of the NCI P-channel LDMOS increase to-188 V and 502.3 V/μm from 75 V and 82.2 V/μm of the conventional P-channel LDMOS with the same thicknesses SOI layer and the buried oxide layer,respectively.The influences of structure parameters on the proposed device characteristics are investigated by simulation.Moreover,compared with the conventional device,the proposed device exhibits low special on-resistance.     

New CMOS compatible super junction LDMOST with n-type buried layer

A new super-junction lateral double diffused MOSFET (LDMOST) structure is designed with n-type charge compensation layer embedded in the p$^{ - }$-substrate near the drain to suppress substrate-assisted depletion effect that results from the compensating charges imbalance between the pillars in the n-type buried layer. A high electric field peak is introduced in the surface by the pn junction between the p$^{ - }$-substrate and n-type buried layer, which given rise to a more uniform surface electric field distribution by modulation effect. The effect of reduced bulk field (REBULF) is introduced to improve the vertical breakdown voltage by reducing the high bulk electric field around the drain. The new structure features high breakdown voltage, low on-resistance and charges balance in the drift region due to n-type buried layer.     

High-voltage SOI lateral MOSFET with a dual vertical field plate

A new silicon-on-insulator(SOI)power lateral MOSFET with a dual vertical field plate(VFP)in the oxide trench is proposed.The dual VFP modulates the distribution of the electric field in the drift region,which enhances the internal field of the drift region and increases the drift doping concentration of the drift region,resulting in remarkable improvements in breakdown voltage(BV)and specific on-resistance(Ron,sp).The mechanism of the VFP is analyzed and the characteristics of BV and Ron,spare discussed.It is shown that the BV of the proposed device increases from 389 V of the conventional device to 589 V,and the Ron,sp decreases from 366 m·cm2to 110 m·cm2.     

Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (R S,on) silicon-on-insulator (SOI) trench MOSFET (metal-oxide-semiconductor-field-effect-transistor) with a reduced cell pitch is proposed.The lateral MOSFET features multiple trenches:two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET).Firstly,the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si;secondly,the oxide trenches cause multiple-directional depletion,which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer.Both of them result in a high breakdown voltage (BV).Thirdly,the oxide trenches cause the drift region to be folded in the vertical direction,leading to a shortened cell pitch and a reduced R S,on.Fourthly,the trench gate extended to the BOX further reduces R S,on,owing to the electron accumulation layer.The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm,and R S,on decreases from 419 m · cm 2 to 36.6 m · cm 2.The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.     

具有P型覆盖层新型超级结横向双扩散功率器件

为了设计功率集成电路所需要的低功耗横向双扩散金属氧化物半导体器件(lateral double-diffused MOSFET), 在已有的N型缓冲层超级结LDMOS(N-buffered-SJ-LDMOS)结构基础上, 提出了一种具有P型覆盖层新型超级结LDMOS结构(P-covered-SJ-LDMOS). 这种结构不但能够消除传统的N沟道SJ-LDMOS由于P型衬底产生的衬底辅助耗尽问题, 使得超级结层的N区和P区的电荷完全补偿, 而且还能利用覆盖层的电荷补偿作用, 提高N型缓冲层浓度, 从而降低了器件的比导通电阻. 利用三维仿真软件ISE分析表明, 在漂移区长度均为10 μm的情况下, P-covered-SJ-LDMOS的比导通电阻较一般SJ-LDMOS结构降低了59%左右, 较文献提出的N型缓冲层 SJ-LDMOS(N-buffered-SJ-LDMOS)结构降低了43%左右.     

A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques

We present a new technique to achieve uniform lateral electric field and maximum breakdown voltage in lateral double-diffused metal-oxide-semiconductor transistors fabricated on silicon-on-insulator substrates. A linearly increasing drift-region thickness from the source to the drain is employed to improve the electric field distribution in the devices. Compared to the lateral linear doping technique and the reduced surface field technique, twodimensional numerical simulations show that the new device exhibits reduced specific on-resistance, maximum off- and on-state breakdown voltages, superior quasi-saturation characteristics and improved safe operating area.     

Effects of trench oxide and field plates on the breakdown voltage of SOI LDMOSFET

To improve the breakdown voltage, we propose a SOI-based LDMOSFET with a trench structure in the drift region. Due to the trench oxide and underneath boron implanted layer, the surface electric field in the drift region effectively reduced. These effects resulted in the increment of breakdown voltage for the trenched LDMOS more than 100 V compared with the conventional device. However, the specific on-resistance, which has a trade-off relationship, is slightly increased. In addition to the trench oxide on the device performance, we also investigated the influence of n− drift to n+ drain junction spacing on the off-state breakdown voltage. The measured breakdown voltages were varied more than 50 V with different n− to n+ design spaces and achieved a maximum value at L_DA = 2.0 μm. Moreover, the influence of field plate on the breakdown voltage of trench LDMOSFET was investigated. It is found that the optimum drain field plate over the field oxide is 8 μm.     

New trench gate power MOSFET with high breakdown voltage and reduced on-resistance using a SiGe zone in drift region

High breakdown voltage and reduced on-resistance are desired characteristics in power MOSFETs. In order to obtain an excellent performance of Trench Gate Power MOSFET, we have proposed a new structure in which a SiGe zone is incorporated in the drift region to reduce on-resistance. Also, the buried oxide is considered in the drift region that surrounds the SiGe zone to increase breakdown voltage. The proposed structure is called a SiGe Zone Trench Gate MOSFET (SZ-TG). Our simulation with two dimensional simulator shows that by reducing an electric field and controlling the effects of parasitic BJT transistor in the SZ-TG structure, we can expand power applications of trench gate power structures.