An application of half-terrace model to surface ripening of non-bulk GaAs layers

In order to predict the actual quantity of non-bulk GaAs layers after long-time homoepitaxy on GaAs （001） by theo- retical calculation, a half-terrace diffusion model based on thermodynamics is used to calculate the ripening time of GaAs layers to form a fiat morphology in annealing. To verify the accuracy of the calculation, real space scanning tunneling microscopy images of GaAs surface after different annealing times are obtained and the roughness of the GaAs surface is measured. The results suggest that the half terrace model is an accurate method with a relative error of about 4.1%.     

测定GaAs(001)衬底上InAs的生长速率

报道了间接测定InAs生长速率的方法.通过设置不同Ga源温度,固定In源温度;和固定Ga源温度,设置不同In源温度,在GaAs(001)衬底上生长GaAs与InGaAs,用RHEED强度振荡测定GaAs与InGaAs的生长速率.验证了InGaAs的生长速率为GaAs的生长速率与InAs的生长速率之和,得到了In源温度在845～880℃时InAs的生长速率曲线.     

Step instability of the In0.2Ga0.8As （001） surface during annealing

Anisotropic evolution of the step edges on the compressive-strained In0.2Ga0.8 As/GaAs(001) surface has been investigated by scanning tunneling microscopy (STM). The experiments suggest that step edges are indeed sinuous and protrude somewhere a little way along the [110] direction, which is different from the classical waviness predicted by the theoretical model. We consider that the monatomic step edges undergo a morphological instability induced by the anisotropic diffusion of adatoms on the terrace during annealing, and we improve a kinetic model of step edge based on the classical Burton–Cabrera–Frank (BCF) model in order to determine the normal velocity of step enlargement. The results show that the normal velocity is proportional to the arc length of the peninsula, which is consistent with the first result of our kinetic model. Additionally, a significant phenomenon is an excess elongation along the [110] direction at the top of the peninsula with a higher aspect ratio, which is attributed to the restriction of diffusion lengths.     

100-nm T-gate InAlAs/InGaAs InP-based HEMTs with f_T = 249 GHz and f_(max) = 415 GHz

InAlAs/InGaAs high electron mobility transistors(HEMTs) on an InP substrate with well-balanced cutoff frequency fTand maximum oscillation frequency fmax are reported. An InAlAs/InGaAs HEMT with 100-nm gate length and gate width of 2 × 50 μm shows excellent DC characteristics, including full channel current of 724 mA/mm, extrinsic maximum transconductance gm.max of 1051 mS/mm, and drain–gate breakdown voltage BVDG of 5.92 V. In addition, this device exhibits fT= 249 GHz and fmax = 415 GHz. These results were obtained by fabricating an asymmetrically recessed gate and minimizing the parasitic resistances. The specific Ohmic contact resistance was reduced to 0.031 Ω·mm. Moreover,the fTobtained in this work is the highest ever reported in 100-nm gate length InAlAs/InGaAs InP-based HEMTs. The outstanding gm.max, fT, fmax, and good BVDG make the device suitable for applications in low noise amplifiers, power amplifiers, and high speed circuits.     

InGaAs薄膜表面的粗糙化过程

采用STM分析InGaAs表面形貌演变研究InGaAs表面的粗糙化和预粗糙化等相变过程, 特别针对In_0.15Ga_0.85As薄膜表面预粗糙化过程进行了深入研究. 发现In_0.15Ga_0.85As薄膜在不同的衬底温度和As等效束流压强下表现出不同的预粗糙化过程. 在低温低As等效束流压强下, 薄膜表面将经历从有序平坦到预粗糙并演变成粗糙的过程, 起初坑的形成是表面形貌演变的主要形式, 随着退火时间的延长, 大量坑和岛的共同形成促使表面进入粗糙状态; 在高温高As等效束流压强下薄膜表面将率先形成小岛, 退火时间延长后小岛逐渐增加并最终达到平衡态, 表面形貌将长期处于预粗糙状态.     

Surface segregation of InGaAs films by the evolution of reflection high-energy electron diffraction patterns

Surface segregation is studied via the evolution of reflection high-energy electron diffraction (RHEED) patterns under different values of As 4 BEP for InGaAs films. When the As 4 BEP is set to be zero, the RHEED pattern keeps a 4×3/(n×3) structure with increasing temperature, and surface segregation takes place until 470 C. The RHEED pattern develops into a metal-rich (4×2) structure as temperature increases to 495 C. The reason for this is that surface segregation makes the In inside the InGaAs film climb to its surface. With the temperature increasing up to 515 C, the RHEED pattern turns into a GaAs(2×4) structure due to In desorption. While the As 4 BEP comes up to a specific value (1.33×10 4 Pa–1.33×10 3 Pa), the surface temperature can delay the segregation and desorption. We find that As 4 BEP has a big influence on surface desorption, while surface segregation is more strongly dependent on temperature than surface desorption.     

Step instability of the surface during Ino.2Gao.sAs （001） annealing

Anisotropic evolution of the step edges on the compressive-strained In0.2Ga0.8As/GaAs（001） surface has been investigated by scanning tunneling microscopy （STM）. The experiments suggest that step edges are indeed sinuous and protrude somewhere a little way along the [110] direction, which is different from the classical waviness predicted by the theoretical model. We consider that the monatomic step edges undergo a morphological instability induced by the anisotropic diffusion of adatoms on the terrace during annealing, and we improve a kinetic model of step edge based on the classical Burton Cabrer-Frank （BCF） model in order to determine the normal velocity of step enlargement. The results show that the normal velocity is proportional to the arc length of the peninsula, which is consistent with the first result of our kinetic model. Additionally, a significant phenomenon is an excess elongation along the [110] direction at the top of the peninsula with a higher aspect ratio, which is attributed to the restriction of diffusion lengths.     

Step instability of the In_0.2Ga_0.8As （001） surface during annealing

Anisotropic evolution of the step edges on the compressive-strained In0.2Ga0.8 As/GaAs(001) surface has been investigated by scanning tunneling microscopy (STM). The experiments suggest that step edges are indeed sinuous and protrude somewhere a little way along the [110] direction, which is different from the classical waviness predicted by the theoretical model. We consider that the monatomic step edges undergo a morphological instability induced by the anisotropic diffusion of adatoms on the terrace during annealing, and we improve a kinetic model of step edge based on the classical Burton–Cabrera–Frank (BCF) model in order to determine the normal velocity of step enlargement. The results show that the normal velocity is proportional to the arc length of the peninsula, which is consistent with the first result of our kinetic model. Additionally, a significant phenomenon is an excess elongation along the [110] direction at the top of the peninsula with a higher aspect ratio, which is attributed to the restriction of diffusion lengths.     

100-nm T-gate InAIAs/InGaAs InP-based HEMTs with fT= 249 GHz and fmax ： 415 GHz

InA1As/InGaAs high electron mobility transistors （HEMTs） on an InP substrate with well-balanced cutoff frequency fT and maximum oscillation frequency frnax are reported. An InA1As/InGaAs HEMT with 100-nm gate length and gate width of 2 × 50 μm shows excellent DC characteristics, including full channel current of 724 mA/mm, extrinsic maximum transconductance gm.max of 1051 mS/mm, and drain-gate breakdown voltage BVDG of 5.92 V. In addition, this device exhibits fT = 249 GHz and fmax = 415 GHz. These results were obtained by fabricating an asymmetrically recessed gate and minimizing the parasitic resistances. The specific Ohmic contact resistance was reduced to 0.031 0.mm. Moreover, the fT obtained in this work is the highest ever reported in 100-nm gate length InA1As/InGaAs InP-based HEMTs. The outstanding gm.max, fT, fmax, and good BVDG make the device suitable for applications in low noise amplifiers, power amplifiers, and high speed circuits.