High-performance 4H-SiC p-i-n ultraviolet avalanche photodiodes with large active area

Ultraviolet(UV) detectors with large photosensitive areas are more advantageous in low-level UV detection applications. In this Letter, high-performance 4 H-SiC p-i-n avalanche photodiodes(APDs) with large active area(800 μm diameter) are reported. With the optimized epitaxial structure and device fabrication process,a high multiplication gain of 1.4 × 10~6 is obtained for the devices at room temperature, and the dark current is as low as ～10 p A at low reverse voltages. In addition, record external quantum efficiency of 85.5% at 274 nm is achieved, which is the highest value for the reported Si C APDs. Furthermore, the rejection ratio of UV to visible light reaches about 10~4. The excellent performance of our devices indicates a tremendous improvement for largearea SiC APD-based UV detectors. Finally, the UV imaging performance of our fabricated 4 H-SiC p-i-n APDs is also demonstrated for system-level applications.     

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator (SOI) high performance lateral double-diffusion metal oxide semiconductor (LDMOS) on a compound buried layer (CBL) with a step buried oxide (SBO CBL SOI) is proposed.The step buried oxide locates holes in the top interface of the upper buried oxide (UBO) layer.Furthermore,holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide (LBO) layer.Consequently,the electric fields in both the thin LBO and the thick UBO are enhanced by these holes,leading to an improved breakdown voltage.The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer.Moreover,SBO CBL SOI can also reduce the self-heating effect.     

Transient simulation and analysis of current collapse due to trapping effects in AlGaN/GaN high-electron-mobility transistor

In this paper, two-dimensional(2D) transient simulations of an Al Ga N/Ga N high-electron-mobility transistor(HEMT)are carried out and analyzed to investigate the current collapse due to trapping effects. The coupling effect of the trapping and thermal effects are taken into account in our simulation. The turn-on pulse gate-lag transient responses with different quiescent biases are obtained, and the pulsed current–voltage(I–V) curves are extracted from the transients. The experimental results of both gate-lag transient current and pulsed I–V curves are reproduced by the simulation, and the current collapse due to the trapping effect is explained from the view of physics based on the simulation results. In addition, the results show that bulk acceptor traps can influence the gate-lag transient characteristics of Al Ga N/Ga N HEMTs besides surface traps and that the thermal effect can accelerate the emission of captured electrons for traps. Pulse transient simulation is meaningful in analyzing the mechanism of dynamic current collapse, and the work in this paper will benefit the reliability study and model development of Ga N-based devices.     

Radio-Frequency Performance of Epitaxial Graphene Field-Effect Transistors on Sapphire Substrates

We report dc and the first-ever measured small signal rf performance of epitaxial graphene field-effect transistors （GFETs）, where the epitaxial graphene is grown by chemical vapor deposition （CVD） on a 2-inch c-plane sapphire substrate. Our epitaxial graphene material has a good flatness and uniformity due to the low carbon concentration during the graphene growth. With a gate length Lg = 100 nm, the maximum drain source current Ids and peak transconductance gm reach 0.92 A/mm and 0.143 S/mm, respectively, which are the highest results reported for GFETs directly grown on sapphire. The extrinsic cutoff frequency （fT） and maximum oscillation frequency （fmax） of the device are 12 GHz and 9.5 GHz, and up to 32 GHz and 21.5 GHz after de-embedding, respectively. Our work proves that epitaxial graphene on sapphire substrates is a promising candidate for rf electronics.     

Different influences of Schottky metal on the strain and relative permittivity of barrier layer between AlN/GaN and AlGaN/GaN heterostructure Schottky diodes

Ni/Au Schottky contacts on AlN/GaN and AlGaN/GaN heterostructures are fabricated.Based on the measured current–voltage and capacitance-voltage curves,the polarization sheet charge density and relative permittivity are analyzed and calculated by self-consistently solving Schrdinger’s and Poisson’s equations.It is found that the values of relative permittivity and polarization sheet charge density of AlN/GaN diode are both much smaller than the ones of AlGaN/GaN diode,and also much lower than the theoretical values.Moreover,by fitting the measured forward I–V curves,the extracted dislocations existing in the barrier layer of the AlN/GaN diode are found to be much more than those of the AlGaN/GaN diode.As a result,the conclusion can be made that compared with AlGaN/GaN diode the Schottky metal has an enhanced influence on the strain of the extremely thinner AlN barrier layer,which is attributed to the more dislocations.     

A new analytical model for the surface electric field distribution and breakdown voltage of the SOI trench LDMOS

A new analytical model for the surface electric field distribution and breakdown voltage of the silicon on insulator (SOI) trench lateral double-diffused metal-oxide-semiconductor (LDMOS) is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.     

Large-area 4H-SiC avalanche photodiodes with high gain and low dark current for visible-blind ultraviolet detection

In this Letter, we report large-area(600 μm diameter) 4H-SiC avalanche photodiodes(APDs) with high gain and low dark current for visible-blind ultraviolet detection. Based on the separate absorption and multiplication structure, 4H-SiC APDs passivated with SiN_xinstead of SiO_2 are demonstrated for the first time, to the best of our knowledge. Benefitting from the SiN_x passivation, the surface leakage current is effectively suppressed. At room temperature, high multiplication gain of 6.5 × 10~5 and low dark current density of 0.88 μA∕cm~2 at the gain of 1000 are achieved for our devices, which are comparable to the previously reported small-area Si C APDs.     

Different influences of Schottky metal on the strain and relative permittivity of barrier layer between AIN/GaN and AIGaN/GaN heterostructure Schottky diodes

Ni/Au Schottky contacts on AlN/GaN and AlGaN/GaN heterostructures are fabricated. Based on the measured current-voltage and capacitance-voltage curves, the polarization sheet charge density and relative permittivity are analyzed and calculated by self-consistently solving Schrodinger＇s and Poisson＇s equations. It is found that the values of relative permittivity and polarization sheet charge density of AlN/GaN diode are both much smaller than the ones of AlGaN/GaN diode, and also much lower than the theoretical values. Moreover, by fitting the measured forward 1-V curves, the extracted dislocations existing in the barrier layer of the AlN/GaN diode are found to be much more than those of the AlGaN/GaN diode. As a result, the conclusion can be made that compared with AlGaN/GaN diode the Schottky metal has an enhanced influence on the strain of the extremely thinner AlN barrier layer, which is attributed to the more dislocations.     

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage( 600 V) integrable silicon-on-insulator(SOI) trench-type lateral insulated gate bipolar transistor(LIGBT) with a reduced cell-pitch is proposed.The LIGBT features multiple trenches(MTs):two oxide trenches in the drift region and a trench gate extended to the buried oxide(BOX).Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field(RESURF) effect.Both increase the breakdown voltage(BV).Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop(Von).The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss(Eoff).The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10?3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.     

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) n-channel lateral double-diffused metal-oxide-semiconductor(LDMOS) is proposed and its mechanism is investigated by simulation.The LDMOS has two features:the integration of a planar gate and an extended trench gate(double gates(DGs));and a buried P-layer in the N-drift region,which forms a triple reduced surface field(RESURF)(TR) structure.The triple RESURF not only modulates the electric field distribution,but also increases N-drift doping,resulting in a reduced specific on-resistance(Ron,sp) and an improved breakdown voltage(BV) in the off-state.The DGs form dual conduction channels and,moreover,the extended trench gate widens the vertical conduction area,both of which further reduce the Ron,sp.The BV and Ron,sp are 328 V and 8.8 m.cm2,respectively,for a DG TR metal-oxide-semiconductor field-effect transistor(MOSFET) by simulation.Compared with a conventional SOI LDMOS,a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%.The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit,thereby saving the chip area and simplifying the fabrication processes.