Exploring the effect of width on performance enhancement in NMOSFETs with a silicon-carbon alloy stressor and a tensile stress silicon nitride liner

The stress distribution in the Si channel regions of a SiC source/drain and stressed silicon nitride liner NMOSFETs with various widths were studied using 3D simulations. The mobility enhancement was found to be dominated by the tensile stress along the transport direction. Stress along the width direction was found to have the least effect on the drain current. The compressive stress along the vertical direction perpendicular to the gate oxide (S_zz) contributes significantly to the mobility enhancement and cannot be neglected in NMOSFETs with a width between 0.05 and 1 μm. The impact of width on performance improvements such as the drive current gain was also analyzed.     

Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs

An analytical model for subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs is presented in this paper. Both the drift and diffusion components of current densities are considered for the modeling of subthreshold current. Virtual cathode concept of DG MOSFETs is utilized to model the subthreshold swing of TM-DG MOSFETs. The effect of different length ratios of the three channel regions under three different gate materials of device on the subthreshold current and subthreshold swing of the short-channel TM-DG MOSFETs have been discussed. The dependencies of subthreshold current and subthreshold swing on various device parameters have been studied. The simulation data obtained by using the commercially available 2D device simulation software ATLAS™ has been used to validate the present model.     

MHz重复频率脉冲功率技术

采用串联单传输线、并联Blumlein脉冲形成线和高重复频率固体开关等技术路线开展了MHz重复频率脉冲功率技术研究。利用串联单传输线获得了幅度约200 kV,时间间隔约500 ns的双脉冲。利用并联使用的Blumlein系统和特殊设计的汇流/隔离网络获得了幅度约275 kV,时间间隔约500 ns的三脉冲。利用并联MOSFET和感应叠加原理研制了6 kV/2.5 MHz固体调制器。结果表明:3种方式均可以猝发MHz的方式输出高品质的高压脉冲串,可根据实际的需求选择合适技术路线。     

Convective scheme solution of the Boltzmann transport equation for nanoscale semiconductor devices

A model for the simulation of the electron energy distribution in nanoscale metal–oxide–semiconductor field-effect transistor (MOSFET) devices, using a kinetic simulation technique, is implemented. The convective scheme (CS), a method of characteristics, is an accurate method of solving the Boltzmann transport equation, a nonlinear integrodifferential equation, for the distribution of electrons in a MOSFET device. The method is used to find probabilities for use in an iterative scheme which iterates to find collision rates in cells. The CS is also a novel approach to 2D semiconductor device simulation. The CS has been extended to handle boundary conditions in 2D as well as to calculation of polygon overlap for polygons of more than three sides. Electron energy distributions in the channel of a MOSFET are presented.     

6H-SiC肖特基源漏MOSFET的模拟仿真研究

给出了一种新型SiC MOSFET——6H-SiC肖特基源漏MOSFET.这种器件结构制备工艺简单，避 免了长期困扰常规SiC MOSFET的离子注入工艺难度大、退火温度高、晶格损伤大，注入激活 率低等问题.分析了该器件的电流输运机理，并通过MEDICI模拟，给出了SiC肖特基源漏MOSF ET伏安特性以及其和金属功函数、栅氧化层厚度和栅长关系. 关键词： 碳化硅 肖特基接触 MOSFET 势垒高度     

A dynamic model of power metal-oxide-semiconductor field-effect transistor half-bridges for the fast simulation of switching induced electromagnetic emissions

Hard switching of semiconductors is the main source of conducted electromagnetic emissions (EME) in pulse-width modulation (PWM) driven power inverters. The requirements on the electromagnetic compatibility grow with the increasing number of installed electric motor drives and inductive power converters. An accurate prediction of the conducted EME requires a model which considers the switching transition of the power semiconductors and the parasitic elements. This typically leads to complex SPICE models, which are hardly suitable for fast dynamic simulations and model-based controller design. This paper presents a compact mathematical model of a low voltage half-bridge inverter, which is based on large-signal models for the individual components and allows for the fast simulation of the conducted EME and switching losses. The high accuracy of the proposed mathematical model is demonstrated by measurement results. In particular, it is shown that the model is able to accurately predict the conducted electromagnetic emissions up to 100 MHz.     

体硅、SOI及DSOI MOSFET器件级电、热分析

利用简化的半导体电学方程,数值模拟获得了各种电学参数的分布,并结合简化电阻模型,模拟了体硅、SOI及DSOI的MOSFET器件的温度场。结果表明MOSFET器件的沟道,特别是靠近漏的区域电场强度及电流密度等各项电、热特性参数在该区域变化剧烈,是最主要的热源区。     

Design of high-repetition frequency gating circuit for cathode of image intensifier北大核心CSCD

According to the requirements of high repetition frequency, fast edge speed and small pulse width for cathode gating signal by range-gated technology, a cathode high repetition frequency gating circuit using period and multi-stage acceleration was proposed. By combining the RC circuit and the high-speed gate circuit, the time bias circuit unit was cascaded to generate logic pulses with different time sequences, which could respectively control the intermediate stage drive MOSFET to generate three phased drive signals, and the output of the intermediate stage drive was used as input of the output-stage MOSFET to control the acceleration and retention of its on-off process. It was verified by software simulation and board-level test. The test results show that the proposed gating circuit can increase the edge time of output pulse from μs level to 2 ns, and can provide +50 V/−200 V cathode off/on voltage, so as to achieve a repetition frequency ranging from 0~350 kHZ, a duty ratio of 0~100%, a minimum pulse width of 3.7 ns, and a pulse output delay time jitter of about 0.1 ns. It has important guiding significance for improving the minimum pulse width performance of high-speed and high-voltage gating power, the highest working repetition frequency and reducing the power loss of the device. © 2022 Editorial office of Journal of Applied Optics. All rights reserved.     

Physical analysis of normally-off ALD Al2O3/GaN MOSFET with different substrates using self-terminating thermal oxidation-assisted wet etching technique

Based on the self-terminating thermal oxidation-assisted wet etching technique, two kinds of enhancement mode Al$_{2}$O$_{3}$/GaN MOSFETs (metal-oxide-semiconductor field-effect transistors) separately with sapphire substrate and Si substrate are prepared. It is found that the performance of sapphire substrate device is better than that of silicon substrate. Comparing these two devices, the maximum drain current of sapphire substrate device (401 mA/mm) is 1.76 times that of silicon substrate device (228 mA/mm), and the field-effect mobility ($\mu_{\rm FEmax}$) of sapphire substrate device (176 cm$^{2}$/V$\cdot$s) is 1.83 times that of silicon substrate device (96 cm$^{2}$/V$\cdot$s). The conductive resistance of silicon substrate device is 21.2 $\Omega {\cdot }$mm, while that of sapphire substrate device is only 15.2 $\Omega {\cdot }$mm, which is 61% that of silicon substrate device. The significant difference in performance between sapphire substrate and Si substrate is related to the differences in interface and border trap near Al$_{2}$O$_{3}$/GaN interface. Experimental studies show that (i) interface/border trap density in the sapphire substrate device is one order of magnitude lower than in the Si substrate device, (ii) Both the border traps in Al$_{2}$O$_{3}$ dielectric near Al$_{2}$O$_{3}$/GaN and the interface traps in Al$_{2}$O$_{3}$/GaN interface have a significantly effect on device channel mobility, and (iii) the properties of gallium nitride materials on different substrates are different due to wet etching. The research results in this work provide a reference for further optimizing the performances of silicon substrate devices.