小尺寸MOS场效应管弱反型饱和特性

考虑到小尺寸MOS(金属-氧化物-半导体)场效应管耗尽区电荷和空间电荷的减少,推导出了小尺寸MOS场效应管弱反型漏极电流的解析表示式,用来描述漏极饱和电流随漏极电压上升而增大的现象,理论与实验符合得较好。本文结果可用于集成电路的计算机模拟设计中。     

Comparative study of low frequency noise and hot-carrier reliability in SiGe PD SOI pMOSFETs

The stress effect of SiGe pMOSFETs has been investigated to understand the electrical properties of devices fabricated on the Si bulk and PD SOI substrates. A comparison of the drain saturation current (I_D.sat) and maximum transconductance (g_m,max) in both the SiGe bulk and the SiGe PD SOI devices clearly shows that the SiGe PD SOI is more immune from hot-carriers than the SiGe bulk. The stress-induced leakage current (SILC) is hardly detectable in ultra-thin oxide, because the increasing contribution of direct tunneling is comparable to the trap-assisted component. The SiGe PD SOI revealed degraded properties being mainly associated with the detrimental silicon-oxide interface states of the SOI structure.     

A novel 10-nm physical gate length double-gate junction field effect transisto

A novel double-gate （DG） junction field effect transistor （JFET） with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performance with square body design, which relaxes the requirement on silicon film thickness of DG devices. Moreover, due to the structural symmetry, both p-type and n-type devices can be realized on exactly the same structure, which greatly simplifies integration. It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.     

Performance and analytical modelling of halo-doped surrounding gate MOSFETs

Halo structure is added to sub-100 nm surrounding-gate metal-oxide-semiconductor fieldeffect-transistors （MOS- FETs） to suppress short channel effect. This paper develops the analytical surface potential and threshold voltage models based on the solution of Poisson＇s equation in fully depleted condition for symmetric halo-doped cylindrical surrounding gate MOSFETs. The performance of the halo-doped device is studied and the validity of the analytical models is verified by comparing the analytical results with the simulated data by three dimensional numerical device simulator Davinci. It shows that the halo doping profile exhibits better performance in suppressing threshold voltage roll-off and drain-induced barrier lowering, and increasing carrier transport efficiency. The derived analytical models are in good agreement with Davinci.     

单管体硅,SOI及DSOI MOSFET热分析

本文简单介绍了SOI和 DSOI半导体器件制造技术,并提出了单管体硅,SOI及 DSOI MOSFET的热阻模型。进而对体硅,SOI MOSFET器件,特别是DSOI MOSPET的热学特性进行数值计算,比较并分析了其数值计算结果。     

Analytical analysis of surface potential for grooved-gate MOSFET

The improvement of the characteristics of grooved-gate MOSFETs compared to the planar devices is attributed to the corner effect of the surface potential along the channel. In this paper we propose an analytical model of the surface potential distribution based on the solution of two-dimensional Poisson equation in cylindrical coordinates utilizing the cylinder approximation and the structure parameters such as the concave corner $\theta _0 $. The relationship between the minimum surface potential and the structure parameters is theoretically analysed. Results confirm that the bigger the concave corner, the more obvious the corner effect. The corner effect increases the threshold voltage of the grooved-gate MOSFETs, so the better is the short channel effect (SCE) immunity.     

Schottky barrier MOSFET structure with silicide source/drain on buried metal

In this paper, we propose a novel Schottky barrier MOSFET structure, in which the silicide source/drain is designed on the buried metal (SSDOM). The source/drain region consists of two layers of silicide materials. Two Schottky barriers are formed between the silicide layers and the silicon channel. In the device design, the top barrier is lower and the bottom is higher. The lower top contact barrier is to provide higher {on-state} current, and the higher bottom contact barrier to reduce the off-state current. To achieve this, ErSi is proposed for the top silicide and CoSi₂ for the bottom in the n-channel case. The 50~nm n-channel SSDOM is thus simulated to analyse the performance of the SSDOM device. In the simulations, the top contact barrier is 0.2e~V (for ErSi) and the bottom barrier is 0.6eV (for CoSi₂. Compared with the corresponding conventional Schottky barrier MOSFET structures (CSB), the high on-state current of the SSDOM is maintained, and the off-state current is efficiently reduced. Thus, the high drive ability (1.2mA/μm at V_ds=1V, V_gs=2V) and the high I_on/I_min ratio (10⁶) are both achieved by applying the SSDOM structure.     

高k栅介质GeOI金属氧化物半导体场效应管阈值电压和亚阈斜率模型及其器件结构设计

通过求解沟道与埋氧层的二维泊松方程,同时考虑垂直沟道与埋氧层方向的二阶效应,建立了高κ栅介质GeOI金属氧化物半导体场效应管(MOSFET)的阈值电压和亚阈斜率解析模型,研究了器件主要结构参数对器件阈值特性、亚阈特性、短沟道效应、漏极感应势垒降低效应及衬偏效应的影响,提出了优化器件性能的结构参数设计原则及取值范围,模拟结果与TCAD仿真结果符合较好,证实了模型的正确性与实用性。     

Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO₂ than SiO₂ in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, I_ON/I_OFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO₂, DIBL shows a reduction of 61.5% over SiO₂. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO₂ when compared to SiO₂. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO₂ based device. From the analysis, it is found that HfO₂ will be a better alternative for the future nanoscale device.