SiC电子输运特性的Monte Carlo数值模拟

利用系综MonteCarlo法研究了2H ,4H和6HSiC的电子输运特性.在模拟中考虑了对其输运过程有着重要影响的声学声子形变势散射、极化光学声子散射、谷间声子散射、电离杂质散射以及中性杂质散射.通过计算,获得了低场下这几种不同SiC多型电子迁移率同温度的关系,并以4H SiC为例,重点分析了中性杂质散射的影响.最后对高场下电子漂移速度的稳态和瞬态变化规律进行了研究.将模拟结果同已有的实验数据进行了比较,发现当阶跃电场强度为10×106V·cm-1时,4H Sic电子横向瞬态速度峰值接近33×107cm·s^-1,6H Sic接近30×107cm·s^-1.     

新型Si3N4层部分固定正电荷AlGaN／GaNHEMTs器件耐压分析

为了优化传统AlGaN／GaNhighelectronmobilitytransistors结构表面电场分布,提高器件击穿电压和可靠性,本文利用不影响AlGaN／GaN异质结极化效应的Si3N4钝化层电荷分布,提出了一种sbN4钝化层部分固定正电荷AIGaN／GaNhighelectronmobilitytransistors新结构．SiaN4钝化层中部分固定正电荷通过电场调制效应使表面电场分布中产生新的电场峰而趋于均匀．新电场峰使得新结构栅边缘和漏端高电场有效降低,器件击穿电压从传统结构的296V提高到新结构的650V,而且可靠性改善．通过Si3N4与AlGaN界面横、纵向电场分布,说明了产生表面电场峰的电场调制效应,为设计SiaN4层部分固定正电荷新结构提供了科学依据．Si3N4钝化层部分固定正电荷的补偿作用,使沟道二维电子气浓度增加,导通电阻减小,输出电流提高．     

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering(DIBL) effect has been obtained by solving the two-dimensional(2D) Poisson’s equation for the dual-channel 4H-SiC MESFET(DCFET).Using this analytical model,we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET,which characterize the DIBL effect.The results show that they are significantly dependent on the drain bias,gate length as well as the thickness and doping concentration of the two channel layers.Based on this analytical model,the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.     

Microwave damage susceptibility trend of a bipolar transistor as a function of frequency

We conduct a theoretical study of the damage susceptibility trend of a typical bipolar transistor induced by a high-power microwave (HPM) as a function of frequency. The dependences of the burnout time and the damage power on the signal frequency are obtained. Studies of the internal damage process and the mechanism of the device are carried out from the variation analysis of the distribution of the electric field, current density, and temperature. The investigation shows that the burnout time linearly depends on the signal frequency. The current density and the electric field at the damage position decrease with increasing frequency. Meanwhile, the temperature elevation occurs in the area between the p-n junction and the n-n + interface due to the increase of the electric field. Adopting the data analysis software, the relationship between the damage power and frequency is obtained. Moreover, the thickness of the substrate has a significant effect on the burnout time.     

Simulation and experimental study of high power microwave damage effect on AlGaAs/InGaAs pseudomorphic high electron mobility transistor

The high power microwave(HPM) damage effect on the Al Ga As/In Ga As pseudomorphic high electron mobility transistor(p HEMT) is studied by simulation and experiments. Simulated results suggest that the HPM damage to p HEMT is due to device burn-out caused by the emerging current path and strong electric field beneath the gate. Besides, the results demonstrate that the damage power threshold decreases but the energy threshold slightly increases with the increase of pulse-width, indicating that HPM with longer pulse-width requires lower power density but more energy to cause the damage to p HEMT. The empirical formulas are proposed to describe the pulse-width dependence. Then the experimental data validate the pulse-width dependence and verify that the proposed formula P = 55τ-0.06 is capable of quickly and accurately estimating the HPM damage susceptibility of p HEMT. Finally the interior observation of damaged samples by scanning electron microscopy(SEM) illustrates that the failure mechanism of the HPM damage to p HEMT is indeed device burn-out and the location beneath the gate near the source side is most susceptible to burn-out, which is in accordance with the simulated results.     

Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit

The through silicon via （TSV） technology has proven to be the critical enabler to realize a three-dimensional （3D） gigscale system with higher performance but shorter interconnect length. However, the received digital signal after trans- mission through a TSV channel, composed of redistribution layers （RDLs）, TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflec- tion of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient （$11） and signal transmission coefficient （$21） are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance （RLGC） elements of the TSV channel are iterated from scattering （S）-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure （HFSS） simulation software by Ansoft.     

多个硅通孔引起的热应力对迁移率和阻止区的影响

本文主要讨论了多个硅通孔引起的热应力对迁移率和阻止区的影响, 得到了器件沟道沿[100]方向时, 硅通孔之间的角度和间距对电子迁移率和阻止区的影响. 设定两种阻止区区域, 即迁移率变化分别为5%和10%的区域, 且主要考虑相邻TSV之间的区域. 仿真结果表明: 当硅通孔和X轴所成角度为π/4时, 电子迁移率变化和阻止区区域最小, 但是可布置器件区域不规则, 不易于布局. 随着间距的增加, 电子迁移率变化和阻止区区域逐渐增大, 趋向于单个TSV的情况; 当角度为0 时, 电子迁移率变化和阻止区区域变大, 可布置器件区域为硅通孔围成的中心小区域上, 形状比较规则, 便于布局. 而且随着间距的增加, 电子迁移率变化和阻止区区域越来越小, 趋向于单个硅通孔的情况.     

基于RLCπ型等效模型的互连网络精确焦耳热功耗计算

基于互连网络的RLC π型等效模型,考虑电感的屏蔽作用和非理想的阶跃激励,提出了互连线网络在斜阶跃激励下的焦耳热功耗计算方法,极大地简化了互连网络中电流和功耗的表达式. 基于90 nm金属氧化物半导体(CMOS)工艺的互连参数对所提出的计算方法进行了计算和仿真验证,对于上升信号小于1 ns的情况,计算结果与Hspice仿真结果的误差小于3%,具有很高的精度,适合应用于大规模互连网络中的功耗估算和热分析.     

考虑温度分布效应的非对称RLC树时钟偏差研究

提出了一种RLC互连树零时钟偏差构建方法.给出了RLC互连温度非均匀分布及其延时的解析公式,并推导计算了最优的零时钟偏差点,所提模型同时考虑了互连温度非均匀分布、电感效应及不对称互连结构对零时钟偏差点的影响.针对65 nm工艺节点对所提模型进行了仿真验证,结果显示,相较于同类模型,最大误差不超过1%. 关键词： RLC')" href="#">RLC 温度分布 不对称互连结构 零时钟偏差点