排序方式: 共有128条查询结果,搜索用时 31 毫秒
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在200℃温度下进行了700h双层铜互连(M1/M2)的应力迁移加速老化试验, 结合有限元分析和聚焦离子束(focused-ion-beam,简称FIB)技术研究了通孔直径分别为500和350nm的铜互连应力诱生空洞失效现象, 探讨了应力诱生空洞的形成机理, 并分析了通孔尺寸对铜互连应力迁移的影响. 结果表明,M1互连应力和应力梯度在通孔底部边缘处达到极大值. 应力梯度在应力诱生空洞成核过程中起主导作用, 由张应力产生的过剩空位在应力梯度作用下沿Cu M1/SiN界面作扩散运动并在应力梯度极大值处成核生长成空洞. 由于M1互连应力沿横向方向变化较快, 因此应力诱生空洞的横向生长速率较大. 当通孔直径增大时,互连应力和应力梯度值增大, 并导致应力诱生空洞的生长速率上升.
关键词:
铜互连
应力迁移
应力诱生空洞
失效 相似文献
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提出了一种基于扩散-蠕变机制的空洞生长模型, 结合应力模拟计算和聚焦离子束分析技术研究了Cu互连应力诱生空洞失效现象, 探讨了应力诱生空洞的形成机制并分析了空洞生长速率与温度、应力梯度和扩散路径的关系. 研究结果表明, 在Cu M1互连顶端通孔拐角底部处应力和应力梯度达到极大值并观察到空洞出现. 应力梯度是决定空洞成核位置及空洞生长速率的关键因素. 应力迁移是空位在应力梯度作用下沿主导扩散路径进行的空位积聚与成核现象, 应力梯度的作用与扩散作用随温度变化方向相反, 并存在一个中值温度使得应力诱生空洞速率达到极大值.
关键词:
Cu互连
应力迁移
应力诱生空洞
失效 相似文献
93.
采用S iH4-C3H8-H2气体反应体系在S iO2/S i复合衬底上进行了S iC薄膜的APCVD生长。实验结果表明,H2表面预处理温度过高或时间过长会导致衬底表面S iO2层熔化再结晶或被腐蚀掉。通过“先硅化再碳化”的工艺方法可以较好地解决S iO2/S i复合衬底上S iC成核困难以及粘附性差的问题,同时还可以有效抑制S iO2中的O原子向S iC生长膜扩散。选择预处理温度和薄膜生长温度为1180℃、H2预处理、S iH4硅化和C3H8碳化时间均为30 s的最佳生长条件时,可以得到<111>晶向择优生长的多晶3C-S iC外延薄膜,薄膜生长速率约为2.0~2.5nm/m in. 相似文献
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Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit (3D IC) is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip (SOC) is established by evaluating the constraints of 1) wiring resource, 2) wiring bandwidth, and 3) wiring noise. In comparison to a two-dimensional integrated circuit (2D IC) in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design. 相似文献
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针对VLSI设计中存在的互连电感效应、热电耦合以及互连温度分布的问题,提出一种缓冲器插入延时优化方法.首先根据互连温度分布的特点得出其电阻模型和延时模型,通过延时、功耗和温度之间的热电耦合效应求得考虑互连温度分布的缓冲器插入最优化延时,利用Matlab软件求得最佳优化结果.采用该方法针对45 nm工艺节点的缓冲器插入进行分析和验证,证实了方法的有效性.研究表明,忽略互连电感效应会高估芯片的优化延时,忽略互连温度分布会低估芯片的优化延时,在全局互连尺寸较小(线宽为245 nm)时,忽略互连温度分布会低估互连延时8.71%. 相似文献
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A novel interconnect-optimal repeater insertion model with target delay constraint in 65nm CMOS 下载免费PDF全文
Repeater optimization is the key for SOC (System on Chip)
interconnect delay design. This paper proposes a novel optimal model
for minimizing power and area overhead of repeaters while meeting
the target performance of on-chip interconnect lines. It also
presents Lagrangian function to find the number of repeaters and
their sizes required for minimizing area and power overhead with
target delay constraint. Based on the 65 nanometre CMOS technology,
the computed results of the intermediate and global lines show that
the proposed model can significantly reduce area and power of
interconnected lines, and the better performance will be achieved
with the longer line. The results compared with the reference paper
demonstrate the validity of this model. It can be integrated into
repeater design methodology and CAD (computer aided design) tool for
interconnect planning in nanometre SOC. 相似文献