基于双电源电压和双阈值电压的全局互连性能优化

基于双电源电压和双阈值电压技术,提出了一种优化全局互连性能的新方法.文中首先定义了一个包含互连延时、带宽和功耗等因素的品质因子用以描述全局互连特性,然后在给定延时牺牲的前提下,通过最大化品质因子求得优化的双电压数值用以节省功耗.仿真结果显示,在65 nm工艺下,针对5%,10%和20%的允许牺牲延时,所提方法相较于单电压方法可分别获得27.8%,40.3%和56.9%的功耗节省.同时发现,随着工艺进步,功耗节省更加明显.该方法可用于高性能全局互连的优化和设计. 关键词： 全局互连 双电源电压 双阈值电压 功耗     

The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al2O3 as the gate dielectric

A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al₂O₃ as the gate dielectric, deposited by atomic layer deposition on the epitaxial layer of a 4H-SiC (0001) 8⁰N-/N+ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al₂O₃ gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties (1×10¹⁴ cm^-2) and low gate-leakage current (I_G = 1 × 10^-3 A/cm^-2@E_ox = 8 MV/cm). Analysis of the current conduction mechanism on the deposited Al₂O₃ gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim (FN) tunneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al₂O₃ is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.     

CMOS反相器的快上升沿强电磁脉冲损伤特性（英文）

随着电磁环境的日益复杂,保证集成电路(IC)的可靠性成为一个巨大的挑战。在此基础上,通过对CMOS反相器的仿真和实验研究,研究了快上升沿电磁脉冲(EMP)引起的陷阱辅助隧穿(TAT)效应。对此进行了详细的机理分析用于解释其物理损伤过程。EMP感应电场在氧化层中产生陷阱和泄漏电流,从而导致器件的输出退化和热失效。建立了退化和失效的理论模型,以描述输出退化及热积累对EMP特征的依赖性。温度分布函数由半导体中的热传导方程导出。基于TLP测试系统进行的相应实验证实了出现的性能退化,与机理分析一致。Sentaurus TCAD的仿真结果表明,EMP引起的损坏是由栅极氧化层中发生的TAT电流路径引起的,这也是器件的易烧坏位置。此外,还讨论了器件失效与脉冲上升沿的关系。本文的机理分析有助于加强其他半导体器件的EMP可靠性研究,可以对CMOS数字集成电路的EMP加固提出建议。     

具有N型缓冲层REBULF Super Junction LDMOS

针对功率集成电路对低损耗LDMOS (lateral double-diffused MOSFET)类器件的要求,在N型缓冲层super junction LDMOS (buffered SJ-LDMOS)结构基础上, 提出了一种具有N型缓冲层的REBULF (reduced BULk field) super junction LDMOS结构. 这种结构不但消除了N沟道SJ-LDMOS由于P型衬底带来的衬底辅助耗尽效应问题, 使super junction的N区和P区电荷完全补偿, 而且同时利用REBULF的部分N型缓冲层电场调制效应, 在表面电场分布中引入新的电场峰而使横向表面电场分布均匀, 提高了器件的击穿电压. 通过优化部分N型埋层的位置和参数, 利用仿真软件ISE分析表明, 新型REBULF SJ-LDMOS 的击穿电压较一般LDMOS提高了49%左右, 较文献提出的buffered SJ-LDMOS结构提高了30%左右. 关键词： lateral double-diffused MOSFET super junction 击穿电压 表面电场     

阶梯AlGaN外延新型Al_(0.25)Ga_(0.75)N/GaNHEMTs击穿特性分析

为了优化AlGaN/GaN HEMTs器件表面电场,提高击穿电压,本文首次提出了一种新型阶梯AlGaN/GaN HEMTs结构.新结构利用AlGaN/GaN异质结形成的2DEG浓度随外延AlGaN层厚度降低而减小的规律,通过减薄靠近栅边缘外延的AlGaN层,使沟道2DEG浓度分区,形成栅边缘低浓度2DEG区,低的2DEG使阶梯AlGaN交界出现新的电场峰,新电场峰的出现有效降低了栅边缘的高峰电场,优化了AlGaN/GaN HEMTs器件的表面电场分布,使器件击穿电压从传统结构的446 V,提高到新结构的640 V.为了获得与实际测试结果一致的击穿曲线,本文在GaN缓冲层中设定了一定浓度的受主型缺陷,通过仿真分析验证了国际上外延GaN缓冲层时掺入受主型离子的原因,并通过仿真分析获得了与实际测试结果一致的击穿曲线.     

新型缓冲层分区电场调制横向双扩散超结功率器件

为了突破传统横向双扩散金属-氧化物-半导体器件(lateral double-diffused MOSFET)击穿电压与比导通电阻的极限关系,本文在缓冲层横向双扩散超结功率器件(super junction LDMOS-SJ LDMOS)结构基础上,提出了具有缓冲层分区新型SJ-LDMOS结构.新结构利用电场调制效应将分区缓冲层产生的电场峰引入超结(super junction)表面而优化了SJ-LDMOS的表面电场分布,缓解了横向LDMOS器件由于受纵向电场影响使横向电场分布不均匀、横向单位耐压量低的问题.利用仿真分析软件ISE分析表明,优化条件下,当缓冲层分区为3时,提出的缓冲层分区SJ-LDMOS表面电场最优,击穿电压达到饱和时较一般LDMOS结构提高了50%左右,较缓冲层SJ-LDMOS结构提高了32%左右,横向单位耐压量达到18.48 V/μm.击穿电压为382 V的缓冲层分区SJ-LDMOS,比导通电阻为25.6 mΩ·cm2,突破了一般LDMOS击穿电压为254 V时比导通电阻为71.8 mΩ·cm2的极限关系.     

Effects of gate-buffer combined with a p-type spacer structure on silicon carbide metalben semiconductor field-effect transistors

An improved structure of silicon carbide metal-semiconductor field-effect transistors (MESFET) is proposed for high power microwave applications. Numerical models for the physical and electrical mechanisms of the device are presented, and the static and dynamic electrical performances are analysed. By comparison with the conventional structure, the proposed structure exhibits a superior frequency response while possessing better DC characteristics. A p-type spacer layer, inserted between the oxide and the channel, is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge. Meanwhile, a lightly doped n-type buffer layer under the gate reduces depletion in the channel, resulting in an increase in the output current and a reduction in the gate-capacitance. The structural parameter dependences of the device performance are discussed, and an optimized design is obtained. The results show that the maximum saturation current density of 325 mA/mm is yielded, compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET, leading to an increase of 79% in the output power density. In addition, improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET, respectively.     

反位缺陷对碳化硅纳米管电子结构和光学性质影响研究

采用基于密度泛函理论的第一性原理计算对含有反位缺陷（5,5）单壁碳化硅纳米管的电子结构和光学性质进行了研究.纳米管进行结构优化的结果显示,C_Si缺陷在纳米管表面形成了凹陷,Si_C缺陷形成了凸起;反位缺陷在纳米管的导带底附近形成了缺陷能级,使纳米管表现出n型导电的特点,由价带顶到缺陷能级的跃迁,在垂直和平行于纳米管管轴方向上形成了新的介电峰.