微波低噪声晶体管电磁脉冲敏感端对研究

 在研究电磁脉冲对微电子器件作用效应的过程中，针对三种不同型号的微波低噪声硅半导体器件进行了电磁脉冲（静电放电和方波电磁脉冲）直接注入的试验，结果发现该类器件对电磁脉冲最敏感的端对并不是EB结（发射极-基极），而是CB结（集电极-基极）。通过对器件结构与放电过程的分析，分别得出了CB结、EB结的损伤机理：随放电电压的增大，热载流子撞击界面，使流经界面处的少数载流子复合速度增加，少数载流子在界面处及界面附近被复合，从而降低了器件的电流放大系数。而无论从哪个结注入，器件完全失效均是由热二次击穿造成。从而更进一步地证明了CB结比EB结更敏感。     

人体静电放电对有机发光二极管的影响

研究了静电放电（ESD）人体模式（HBM）下的脉冲应力对有机发光二极管（OLED）的性能及寿命的影响,并讨论了相应的物理机制。对比分析了4组OLED在施加ESD放电为0,200,800,1 600 V前后的电学和光学特性,并进行了相应的寿命测试分析。研究发现,OLED器件的光谱对ESD不敏感,随着冲击电压的增大,由于静电打击对载流子的短期抑制效应,OLED的亮度出现轻微下降。在静电冲击电压为200 V和800 V时,伏安特性没有发生变化;当静电冲击电压增至1 600 V时,反向漏电有明显增加。后续的加速寿命实验表明,静电打击对器件的工作寿命没有明显的规律性影响,但是会一定程度提高非本质老化失效的概率。     

静电放电对GaN基功率型LED老化特性的影响

对GaN基蓝光功率型LED在老化前和老化期间施加反向人体模式静电放电(ESD),并对静电打击前后及老化前后的LED光学电学参数进行分析。实验结果及理论分析表明,ESD使LED芯片有源层及限制层中产生缺陷,最终导致电学特性及光学特性的变化。ESD给LED带来的损伤可在老化前期过程中被局部恢复,但随着老化时间推移,电参数漂移程度及光衰幅度不断增大,而老化过程中LED对ESD的敏感度增加,使LED抗ESD能力减弱。     

计算机操作中人体静电放电辐射瞬态电场与磁场的研究

分析了静电放电（ESD）辐射场的偶极子模型。用高采样速率数字示波器和定做的宽带电磁与磁场探头测量了计算机操作中人体静电放电产生的瞬态电场与磁场。用FFT分析了静电放电辐射场的频谱。研究了静民放电辐射场对某电路高频信号的影响。研究结果表明,即使是很低电压（2kV）的静电放电,其辐射近场的电场达几百V/m,磁场可达几十A/m静电放电辐射场的频谱极宽,从数兆赫到数千兆赫。静电放电对高频电路的试验结果表明,若不采取有效的防护措施,人体静电放电辐射电磁场会对电路造成一定的影响,如对集成电路与元器件造成“潜在效应”的损害,对电路造成电磁干扰,甚至损坏电子器件。     

隧道场效应晶体管静电放电冲击特性研究

随着器件尺寸的不断减小,集成度的逐步提高,功耗成为了制约集成电路产业界发展的主要问题之一.由于通过引入带带隧穿机理可以实现更小的亚阈值斜率,隧道场效应晶体管(TFET)器件已成为下一代集成电路的最具竞争力的备选器件之一.但是TFET器件更薄的栅氧化层、更短的沟道长度容易使器件局部产生高的电流密度、电场密度和热量,使得其更容易遭受静电放电(ESD)冲击损伤.此外,TFET器件基于带带隧穿机理的全新工作原理也使得其ESD保护设计面临更多挑战.本文采用传输线脉冲的ESD测试方法深入分析了基本TFET器件在ESD冲击下器件开启、维持、泄放和击穿等过程的电流特性和工作机理.在此基础之上,给出了一种改进型TFET抗ESD冲击器件,通过在源端增加N型高掺杂区,有效的调节接触势垒形状,降低隧穿结的宽度,从而获得更好的ESD设计窗口.     

静放电电磁脉冲模拟装置

介绍了静电放电电磁脉冲（ESD EMP）的特性，研究了用ESD模拟器产生ESD EMP的方法，并给出了ESD EMP的时域波形和频谱。在研究ESD模拟器的基础上，首次通过ESD模拟器和GTEM室的结合，在GTEM室内产生了均匀的，重复性和线性好的ESD EMP。实验表明，用这种能够实验对静电放电电磁脉冲的实验室模拟，实验了人们用GTEM室产生ESD EMP的梦想。     

静电放电电磁脉冲模拟装置

 介绍了静电放电电磁脉冲（ESD EMP）的特性。研究了用ESD 模拟器产生ESD EMP的方法，并给出了ESD EMP的时域波形和频谱。在研究ESD模拟器的基础上，首次通过ESD模拟器和GTEM室的结合，在GTEM室内产生了均匀的、重复性和线性好的ESD EMP。实验表明，用这种装置能够实现对静电放电电磁脉冲的实验室模拟。实现了人们用GTEM室产生ESD EMP的梦想。     

倒装芯片塑料球栅阵列封装器件在外应力下的失效机理

倒装芯片塑料球栅阵列(FC-PBGA)封装形式独特而被广泛应用, 分析研究其在实际应用过程中, 在高温、电、水汽等多种综合环境应力条件作用下的失效机理对提高其应用可靠性有重要意义. 本文对0.13 μm 6层铜布线工艺的FC-PBGA FPGA器件, 通过暴露器件在以高温回流焊过程中的热-机械应力为主的综合外应力作用下的失效模式, 分析与失效模式相对应的失效机理. 研究结果表明, FC-PBGA器件组装时的内外温差及高温回流焊安装过程中所产生的热-机械应力是导致失效的根本原因, 在该应力作用下, 芯片上的焊球会发生再熔融、桥接相邻焊球致器件短路失效; 芯片与基板之间的填充料会发生裂缝分层、倒装芯片焊球开裂/脱落致器件开路失效; 芯片内部的铜/低k互连结构的完整性受损伤而影响FC-PBGA器件的使用寿命.     

GGMOS型静电放电防护器件的高功率微波效应北大核心CSCD

采用基于半导体漂移扩散模型的数值模拟软件对高功率微波(HPM)作用下GGMOS型的静电放电(ESD)防护器件效应进行了数值模拟研究。对ESD器件在HPM作用下的响应特性及器件内部的物理图像进行了数值模拟。数值模拟的结果表明,外部注入HPM信号的幅值和频率是影响ESD器件的因素,在加载30ns脉宽的HPM脉冲作用下,器件内部达到的最高温度与信号幅值成正指数关系。在给ESD注入相同幅值的HPM信号时,频率越大,器件达到失效温度所需要的时间越长。     

GaN基白光LED可靠性研究与失效分析

针对LED样品检测中的样品短路失效、LED光源黑化、光通量下降和芯片表面通孔异常现象,采用金相切片、机械微操、静电测试等方式结合扫描电镜和能谱仪（EDS）等表征手段对失效机制进行了分析,揭示了LED失效原因。包括镀层银离子与杂质硫离子导致光源黑化;芯片抗静电电压低,部分样品发生静电击穿;失效芯片通孔下面的Ni-Sn共晶层存在大量空洞,使得复杂结构的芯片通孔应力不均,样品工作时芯片表面开裂破碎,从而导致PN结短路失效;封装胶中残存的杂质离子腐蚀芯片负电极导致电极脱落而出现漏电、光衰和死灯等现象。     

Detection of nanoscale ESD effect on GMR head signal using the wavelet transform technique: HBM and CDM cases

An electrical signal anomaly is an undesired signal and is difficult to detect by a commercial instrument due to its short duration and unpredictable fault on a signal. Since a GMR recording head is a stack of nanometer thick multilayers, in particular, a magnetic layer and conductor layers, for magnetic insulating spacers, it is very sensitive to electron movements. Visible damage is understandable and protectable but latent failure cannot be measured. It is possibly observed by using frequency-domain apparatus but certainly it is not real-time detection. Therefore, in order to detect a latent failure head affected by ESD in the time domain, current conventional instruments are ineffective. In this study, the wavelet transform technique using the 4th order Daubechies is proposed to detect the glitches on a magnetic recording head signal in the time domain. It is found that the glitches occur when the ESD level of the charged device model (CDM) and human body model (HBM) on giant magnetoresistive (GMR) heads are in ranges of 6–15 V and 40–120 V, respectively. The electrical test parameters and scanning electron microscope (SEM) photo of the recording heads show no visible change in reader sensor. To ensure the results, the GMR damage is observed by SEM when the CDM-ESD and HBM-ESD are 10 V and 130 V, respectively. The glitches in the magnetic response signal of the GMR head are found to increase when the ESD level is increased. Thus, the Daubechies wavelet transform technique can be a novel approach to detect the pre-degradation of a GMR head due to an ESD effect.     

Analysis of charge injection processes including ESD in MEMS

The effect of charge injection due to human body model (HBM) electrostatic discharge (ESD), charged device model (CDM) ESD and triboelectrification in capacitive microelectromechanical systems' (MEMS) structures is analyzed. The results show that as feature size is reduced, the effect remains constant for charging by triboelectrification. However, HBM ESD injected charge produces a change which is inversely proportional to the square of the gap separation and CDM ESD injected charge produces a change which is inversely proportional to the square of the plate area.     

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN

Ultra-high-voltage(UHV) junction field-effect transistors(JFETs) embedded separately with the lateral NPN(JFETLNPN), and the lateral and vertical NPN(JFET-LVNPN), are demonstrated experimentally for improving the electrostatic discharge(ESD) robustness. The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-k V human body model(HBM) test. The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET. The failure analysis of the devices is performed with scanning electron microscopy, and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities. Finally,the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation, and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN,because the vertical NPN has a better electron collecting capacity. The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.     

Instability of storage and temperature increment in nanopillars due to human body model electrostatic discharge

MRAM relevant to current induced magnetization switching (CIMS) is studied due to thermal increment caused by CIMS. In this paper, the instability of storage and the thermal increment caused by the transient current from the HBM ESD in nanopillars of MRAM are studied. We determine the voltage which can cause erroneous switching in MRAM by inducing CIMS. The finite element method is used to calculate the temperature increase caused by the discharge. Results indicate that this voltage is not sufficient to cause permanent physical or magnetic damage to MRAMs but only affects the reliability of the stored information.     

Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 μm CMOS process

ESD protection for radio frequency (RF) applications must deal with good ESD performance, minimum capacitance, zero series resistance and good capacitance linearity. In order to fulfill these requirements, different ESD protection strategies for RF applications have been investigated in a 0.18 μm CMOS process. This paper compares different ESD protection devices and shows that a suitable ESD performance target for RF applications (200 fF max, 2 kV HBM) can be reached with a diode network scheme. The optimization of the diodes is then a key point which is detailed. A trade-off has to be found between the ESD performance, the voltage drop during ESD and the parasitic capacitance. Poly as well as shallow trench isolation (STI) bounded diodes have been studied and it appears clearly that a solution based on poly bounded diodes is the best choice.     

Enhanced ESD properties of GaN-based light-emitting diodes with various MOS capacitor designs

High electrostatic discharge (ESD) protection of GaN-based light-emitting diodes (LEDs) has been developed using a metal–oxide semiconductor (MOS) capacitor. This structure is realized by adopting various metal electrode patterns. The MOS capacitor can be implemented by extending the metal line directly from the p-type electrode to the top surface of an SiO₂-capped n-GaN layer near the vicinity of the n-type electrode. By connecting a MOS capacitor in parallel with the GaN-based LED, the negative ESD strike could be significantly increased from 385 to 1075 V of human body mode (HBM).     

InGaZnO薄膜晶体管背板的栅极驱动电路静电释放失效研究

本文通过解析阵列基板栅极驱动(gate driver on array, GOA)电路中发生静电释放(electro-static discharge,ESD)的InGaZnO薄膜晶体管(InGaZnO thin-film transistor, IGZO TFT)器件发现:栅极Cu金属扩散进入了SiN_x/SiO_2栅极绝缘层;源漏极金属层成膜前就发生了ESD破坏;距离ESD破坏区域越近的IGZO TFT,电流开关比越小,直到源漏极与栅极完全短路.本文综合IGZO TFT器件工艺、GOA区与显示区金属密度比、栅极金属层与绝缘层厚度非均匀性分布等因素,采用ESD器件级分析与系统级分析相结合的方法,提出栅极Cu:SiN_x/SiO_2界面缺陷以及这三层薄膜的厚度非均匀分布是导致GOA电路中沟道宽长比大的IGZO TFT发生ESD失效的关键因素,并针对性地提出了改善方案.     

Evaluation of ESD hardness of fingerprint sensor LSIs

We evaluated the electrostatic discharge (ESD) hardness of capacitive fingerprint sensor large scaled integrated circuits (LSIs) with two kinds of ESD test methods.We used three kinds of fingerprint sensor LSIs, i.e., a conventional planar sensor LSI, a sensor LSI with a grounded wall (GND wall) structure where each sensor plate was surrounded by a lattice-like wall, and a sensor where some of the sensor plates had been replaced with GNDs. In human body model (HBM)-based contact discharge tests, the sensor LSI with the GND wall structure and the one with the GNDs demonstrated a high ESD hardness compared with the planar sensor LSI. An air discharge test was also carried out in accordance with IEC61000-4-2 specifications because other ESD tests cannot be used to estimate over ±8 kV. The ESD hardness of the GND wall structure was ±20 kV, whereas that of the other sensor with the GND structure was below ±12 kV. It was evident from our findings that the ESD hardness of sensor LSIs obviously depends on the number of GNDs in the sensor region, their arrangement, and the GND structure, and that the sensor LSI with the GND wall had the highest ESD hardness.