Effects of channel doping concentration and fin dimension variation on self-boosting of channel potential in NAND-type SONOS flash memory array based on bulk-FinFETs

In conducting the operation of the NAND-type flash memory array, program inhibition is performed by self-boosting of the potential of the floating silicon channel. However, the high program voltage substantially affects the adjacent cells sharing either the bit-line (BL) or the word-line (WL), which results in unwanted program operation, i.e., program disturbance, in the vicinity. In this work, the dependence of self-boosting effect of the channel potential on process variables and device dimensions have been investigated by 3-D device simulation. Through a series of simulations, the process parameters and device dimensions were identified that can provide the optimum condition in self-boosting of the channel potential avoiding such disturbance. The self-boosting effect exhibited a local maximum at the channel doping concentration of 6 × 10¹⁷ boron atoms/cm³ when the Si fin width was 30 nm and the channel length is 100 nm. Also, it is shown that the boosted channel potential displays monotonic increase with channel length, while it decreases monotonically as the silicon fin width becomes thicker at a given channel doping level. The interpretation of these findings utilizes the graphed results with the advanced capacitance model for a FinFET-based nonvolatile flash memory device.     

Shrinking limits of silicon MOSFETs: numerical study of 10 nm scale devices

We have performed numerical modeling of dual-gate ballistic n-MOSFETs with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a self-consistent solution of the full (two-dimensional) electrostatic problem, with account of electric field penetration into the heavily doped electrodes. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4000 mS mm ^− 1or gate modulation of current by more than 8 orders of magnitude, depending on the gate oxide thickness. These characteristics make the devices satisfactory for logic and memory applications, respectively, although their gate threshold voltage is rather sensitive to nanometer-scale variations in the channel length.     

Temperature-dependent conductance of quasi-one-dimensional electrons in a novel constricted channel with corrugated interfaces

Transport properties of a novel quasi-ballistic quantum wire field-effect transistor are studied experimentally and then discussed in relation to a theory for dirty Tomonaga–Luttinger (T–L) liquids. The sample was prepared by constricting lithographically an epitaxially grown In_0.1Ga_0.9As/GaAs quantum well channel, whose bottom interface is corrugated by a quasi-periodic array of multi-atomic steps of 20 nm in periodicity. A quasi-one-dimensional channel of about 200 nm in metallurgical width and in length was formed and its conductance parallel to the steps was measured at temperatures between 4 and 0.3 K as a function of gate voltage. Plateau-like structures substantially lower than 2e²/h were observed. The conductance at each gate voltage decreases sensitively as temperature lowers until it gets nearly constant below a critical temperature. These tendencies are found to be qualitatively consistent with the theory of Ogata and Fukuyama for dirty T–L liquids. The temperature dependence above the critical temperature is found to fit quantitatively with the formula of Ogata and Fukuyama, if the parameters are suitably chosen.     

Fabrication and electrical properties of a carbon nanotube quantum dot

Single-walled carbon nanotubes (SWNTs) were synthesized by pyrolyzing methane (CH₄) at a temperature of 900℃ on SiO₂ substrates pre-coated with iron nano-particles. Electrical contacts were fabricated onto one of the SWNTs by using an electron beam lithography process. Coulomb blockade and single-electron tunnelling characters were found at low temperatures, indicating that the SWNT in-between the electrodes forms a quantum dot. It is found that the Coulomb gap of the quantum dot is about 8.57 meV, and the factor \alpha , which converts the gate voltage to the true electrostatic potential shift, is around 200 for this device.     

All‐optical modulation based on silicon quantum dot doped SiOx:Si‐QD waveguide

All‐optical modulation based on silicon quantum dot doped SiO_x:Si‐QD waveguide is demonstrated. By shrinking the Si‐QD size from 4.3 nm to 1.7 nm in SiO_x matrix (SiO_x:Si‐QD) waveguide, the free‐carrier absorption (FCA) cross section of the Si‐QD is decreased to 8 × 10⁻¹⁸ cm² by enlarging the electron/hole effective masses, which shortens the PL and Auger lifetime to 83 ns and 16.5 ps, respectively. The FCA loss is conversely increased from 0.03 cm⁻¹ to 1.5 cm⁻¹ with the Si‐QD size enlarged from 1.7 nm to 4.3 nm due to the enhanced FCA cross section and the increased free‐carrier density in large Si‐QDs. Both the FCA and free‐carrier relaxation processes of Si‐QDs are shortened as the radiative recombination rate is enlarged by electron–hole momentum overlapping under strong quantum confinement effect. The all‐optical return‐to‐zero on‐off keying (RZ‐OOK) modulation is performed by using the SiO_x:Si‐QD waveguides, providing the transmission bit rate of the inversed RZ‐OOK data stream conversion from 0.2 to 2 Mbit/s by shrinking the Si‐QD size from 4.3 to 1.7 nm.     

Electroluminescence with micro-watt output from ultra-small sized Si quantum dots/amorphous SiO2 multilayers prepared by laser crystallization method

We report the fabrication of Si quantum dots (QDs)/SiO₂ multilayers by using KrF excimer laser (248 nm) crystallization of amorphous Si/SiO₂ multilayered structures on ITO coated glass substrates. Raman spectra and transmission electron microscopy demonstrate the formation of Si QDs and the size can be controlled as small as 1.8 nm. After laser crystallization, Al electrode is evaporated to obtain light emitting devices and the room temperature electroluminescence (EL) can be detected with applying the DC voltage above 8 V on the top gate electrode. The luminescent intensity increases with increasing the applied voltage and the micro-watt light output is achieved. The EL behaviors for samples with different Si dot sizes are studied and it is found that the corresponding external quantum efficiency is significantly enhanced in sample with ultra-small sized Si QDs.     

Single-electron transistor effect in a two-terminal structure

A peculiarity of the single-electron transistor effect makes it possible to observe this effect even in structures lacking a gate electrode altogether. The proposed method can be useful for experimental study of charging effects in structures with an extremely small central island confined between tunnel barriers (like an ≃1 nm quantum dot or a macromolecule probed with a tunneling microscope), where it is impossible to provide a gate electrode for control of the tunnel current. Pis’ma Zh. éksp. Teor. Fiz. 66, No. 7, 507–511 (10 October 1997) Published in English in the original Russian journal. Edited by Steve Torstveit.     

Non-volatile memory effect of a high-density NiSi nano-dots floating gate memory using single triangular-shaped Si nanowire channel

A back-gated nonplanar floating gate device based on buried single triangular-shaped Si nanowire channel (width ～40 nm) and embedded high-density uniform NiSi nano-dots (～1.5×10¹² cm^?2) is demonstrated. Memory properties including memory window, programming/erasing, and retention are evaluated. The transfer and transient characteristics show clear charge injection, storage and removal effects and the associated programming/erasing mechanism based on fringing electric field is studied. Robust room and high temperature retention performance is observed.     

Signature of Kondo effect in silicon quantum dots

We report observation of the Kondo effect in the Coulomb blockade oscillations of an impurity quantum dot (IQD). This IQD is formed in the channel of a 100 nm gate length Silicon MOSFET. The quantitative analysis of the anomalous temperature and voltage dependence for the drain-source current over a series of Coulomb blockade oscillations is performed. It strongly supports the Kondo explanation for the conductance behavior at very low temperature in this standard microelectronics device. Received 13 November 2001 and Received in final form 18 February 2002     

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain(LDD) overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.     

Quantized current in a quantum dot turnstile

We have performed RF experiments on a lateral quantum dot defined in the two dimensional electron gas (2DEG) of a GaAs/AlGaAs heterostructure. The small capacitance of the quantum dot gives rise to single-electron charging effects, which we employed to realize a quantum dot turnstile device. By modulating the tunnel barriers between the quantum dot and the 2DEG leads with two phase-shifted RF signals, we pass an integer number of electrons through the quantum dot per RF cycle. This is demonstrated by the observation of quantized current plateaus at multiples ofef in current-voltage characteristics, wheref is the frequency of the RF signals. When an asymmetry is induced by applying unequal RF voltages, our quantum dot turnstile operates as a single-electron pump producing a quantized current at zero bias voltage.     

Multiple Andreev reflections in a carbon nanotube quantum dot

We report resonant multiple Andreev reflections in a multiwall carbon nanotube quantum dot coupled to superconducting leads. The position and magnitude of the subharmonic gap structure is found to depend strongly on the level positions of the single-electron states which are adjusted with a gate electrode. We discuss a theoretical model of the device and compare the calculated differential conductance with the experimental data.     

量子点浮置栅量子线沟道三栅结构单电子场效应管存储特性的数值模拟

通过建立二维薛定谔方程和泊松方程数值模型,对基于硅量子点浮置栅和硅量子线沟道三栅结构单电子场效应管(FET)存储特性进行了研究.通过在不同尺寸、栅压和不同写入电荷条件下,对硅量子线沟道中电子浓度的二维有限元自洽数值求解,研究了在纳米尺度下硅量子线沟道中量子限制效应和电荷分布对于器件特性的影响.模拟结果发现,沟道的导通阈值电压随着尺寸的缩小而提高,并随浮置栅内存储的电子数目的增加而明显升高.然而,这样的增加趋势在受到纳米尺度沟道中高电荷密度的影响下将出现非线性饱和趋势.进一步研究发现,当沟道尺寸较小时,沟道 关键词： 三栅单电子FET存储器 量子效应 薛定谔方程 泊松方程     

Carrier conduction in a Si-nanocrystal-based single-electron transistor-II. Effect of drain bias

We have successfully fabricated a single-electron transistor based on undoped Si nanocrystals having radii of approximately 3–5 nm. The energy band structure of the Si dot consists of a set of discrete sublevels and a quasi-continuous band. By self-consistently solving the 3D Schrödinger and Poisson equations we have shown that the undoped Si dots between the source and drain are not occupied at zero gate bias. The carrier transport properties observed experimentally at zero gate bias have been well attributed to carrier tunneling through a multiple-step potential barrier between the source and drain junctions. Each step in the potential barrier corresponds to the bottom of the quasi-continuous band in one Si nanocrystal.     

Fabrication of metal/quantum dot/semiconductor structure on silicon substrate

A fabrication technique and optimal growth conditions are reported to develop a Sb-based quantum dot (QD) structure as a nanostructured III–V semiconductor on a silicon substrate. By using solid-source molecular beam epitaxy, high-density (>10¹⁰ cm⁻²) InGaSb QD structures can be obtained under a low growth temperature, which is compatible for use with Si-CMOS processes. We also proposed the construction of a metal/quantum dot/semiconductor (MDS) structure by using the InGaSb QD on a Si substrate. An infrared light emission with a photon energy of 0.95 eV is successfully observed from the fabricated MDS structure under the current injection conditions. It is expected that a MDS structure using a Sb-based QD will be used as a small-sized infrared light source for silicon photonic technology.     

Novel vertical stack HCMOSFET with strained SiGe/Si quantum channel

A novel vertical stack heterostructure CMOSFET is investigated, which is structured by strained SiGe/Si with a hole quantum well channel in the compressively strained Si量子信道 异质结构 CMOSFET 量子论 量子阱strained SiGe/Si, quantum well channel, heterostructure CMOSFET, poly-SiGe gateProject supported by the Preresearch from National Ministries and Commissions (Grant Nos 51408061104DZ01, 51439010904DZ0101).2/2/2006 12:00:00 AM2006-01-022006-03-16A novel vertical stack heterostructure CMOSFET is investigated, which is structured by strained SiGe/Si with a hole quantum well channel in the compressively strained Sil-xGex layer for p-MOSFET and an electron quantum well channel in the tensile strained Si layer for n-MOSFET. The device possesses several advantages including： 1） the integration of electron quantum well channel with hole quantum well channel into the same vertical layer structure; 2） the gate work function modifiability due to the introduction of poly-SiGe as a gate material; 3） better transistor matching; and 4） flexibility of layout design of CMOSFET by adopting exactly the same material lays for both n-channel and p-channel. The MEDICI simulation result shows that p-MOSFET and n-MOSFET have approximately the same matching threshold voltages. Nice performances are displayed in transfer characteristic, transconductance and cut-off frequency. In addition, its operation as an inverter confirms the CMOSFET structured device to be normal and effective in function.     

Two sub-band conductivity of Si quantum well

We report on two sub-band/bi-layer transport in double gate SiO₂–Si–SiO₂ quantum well with 14 nm thick Si layer at 270 mK. At symmetric well potential the experimental sub-band spacing changes monotonically from 2.3 to 0.3 meV when the total electron density is adjusted by gate voltages between 0.7×10¹⁶–. The conductivity is mapped in large gate bias window and it shows strong non-monotonic features. At symmetric well potential and high density these features are addressed to sub-band wave function delocalization in the quantization direction and to different disorder of the top and bottom interfaces of the Si well. In the gate bias regimes close to second sub-band/bi-layer threshold the non-monotonic behavior is interpreted to arise from scattering from the other electron sub-system with localized or low mobility states.     

SINGLE-ELECTRON TRANSISTORS FOR FUTURE APPLICATIONS

Single electron transistors with wire channels are fabricated by a nanoelectrode-pair technique. Their characteristics strongly depend on the channel widths and the voltages on the in-plane gates. A few dips in the Coulomb blockade oscillations were observed at the less positive gate voltages for a device with a 70nm-wide wire due to Coulomb blockade between the coupled dots. By applying negative voltages to the in-plane gates, the oscillations became periodic, which indicated the formation of a single dot in the conducting channel. These gates facilitate fabricating single-electron transistors with single dot structures, which have potential applications on its integration.     

Light Trapping and Down‐Shifting Effect of Periodically Nanopatterned Si‐Quantum‐Dot‐Based Structures for Enhanced Photovoltaic Properties

Periodically nanopatterned Si structures have been prepared by using a nanosphere lithography technique. The formed nanopatterned structures exhibit good anti‐reflection and enhanced optical absorption characteristics. The mean surface reflectance weighted by AM1.5 solar spectrum (300–1200 nm) is as low as 5%. By depositing Si quantum dot/SiO₂ multilayers (MLs) on the nanopatterned Si substrate, the optical absorption is higher than 90%, which is significantly improved compared with the same multilayers deposited on flat Si substrate. Furthermore, the prototype n‐Si/Si quantum dot/SiO₂ MLs/p‐Si heterojunction solar cells has been fabricated, and it is found that the external quantum efficiency is obviously enhanced for nanopatterned cell in a wide spectral range compared with the flat cell. The corresponding short‐circuit current density is increased from 25.5 mA cm^?2 for flat cell to 29.0 mA cm^?2 for nano‐patterned one. The improvement of cell performance can be attributed both to the reduced light loss and the down‐shifting effect of Si quantum dots/SiO₂ MLs by forming periodically nanopatterned structures.     

Ge metal oxide semiconductor field effect transistors with optimized Si cap and HfSiO2 high-k metal gate stacks

High mobility metal-oxide-semiconductor-field-effect-transistors (MOSFETs) are demonstrated on high quality epitaxial Si_0.75Ge_0.25 films selectively grown on Si (100) substrates. With a Si cap processed on Si_0.75Ge_0.25 channels, HfSiO₂ high-k gate dielectrics exhibited low C–V hysteresis (<10 mV), interface trap density (7.5 × 10¹⁰), and gate leakage current (∼10⁻²A/cm² at an EOT of 13.4 Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the Si_0.75Ge_0.25 channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of Si_0.75Ge_0.25 channels, which are major causes of the high off-state current of small band gap energy Si_0.75Ge_0.25 pMOSFETs, by improving gate control over the channel.