Study of valence intersubband absorption in tensile strained Si/SiGe quantum wells

The hole subband structures and effective masses of tensile strained Si/Sil-yGey quantum wells are calculated by using the 6 × 6 k·p method. The results show that when the tensile strain is induced in the quantum well, the light-hole state becomes the ground state, and the light hole effective masses in the growth direction are strongly reduced while the in-plane effective masses are considerable. Quantitative calculation of the valence intersubband transition between two light hole states in a 7nm tensile strained Si/Si0.55Ge0.45 quantum well grown on a relaxed Si0.5Ge0.5 （100） substrates shows a large absorption coefficient of 8400 cm^-1.     

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO7340Q, 7325http://cpb.iphy.ac.cn/CN/10.1088/1674-1056/19/5/057302https://cpb.iphy.ac.cn/CN/article/downloadArticleFile.do?attachType=PDF&id=111774Ge substrate, transistor, HfSiON, hole mobilityProject supported by the National Basic Research Program of China (Grant No.~2006CB302704).Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO$_{x}$ ($1Ge;substrate;transistor;HfSiON;hole;mobilityGe and Si p-channel metal-oxide-semiconductor field-effect-transistors(p-MOSFETs) with hafnium silicon oxynitride(HfSiON) gate dielectric and tantalum nitride(TaN) metal gate are fabricated.Self-isolated ring-type transistor structures with two masks are employed.W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately.Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor(MOS) capacitors may be caused by charge trapping centres in GeOx(1 < x < 2).Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method.The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V.s) and 81.0 cm2/(V.s),respectively.Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.     

量子阱Si/SiGe/Sip型场效应管阈值电压和沟道空穴面密度模型

Si材料中较低的空穴迁移率限制了Si互补金属氧化物半导体器 件在高频领域的应用. 针对SiGe p型金属氧化物半导体场效应管(PMOSFET)结构, 通过求解纵向一维泊松方程,得到了器件的纵向电势分布, 并在此基础上建立了器件的阈值电压模型,讨论了Ge组分、缓冲层厚度、 Si帽层厚度和衬底掺杂对阈值电压的影响.由于SiGe沟道层较薄, 计算中考虑了该层价带势阱中的量子化效应. 当栅电压绝对值过大时, 由于能带弯曲和能级分裂造成SiGe沟道层中的空穴会越过势垒到达Si/SiO₂界面, 从而引起器件性能的退化. 建立了量子阱SiGe PMOSFET沟道层的空穴面密度模型, 提出了最大工作栅电压的概念, 对由栅电压引起的沟道饱和进行了计算和分析. 研究结果表明,器件的阈值电压和最大工作栅压与SiGe层Ge组分关系密切, Ge组分的适当提高可以使器件工作栅电压范围有效增大.     

小尺寸单轴应变Si PMOS沟道晶面/晶向选择实验新发现

小尺寸单轴应变Si p型金属氧化物半导体(PMOS)沟道反型层迁移率与晶面/晶向密切相关,应变PMOS优化设计时应合理选择沟道的晶面/晶向.目前,文献已有1.5 GPa应力强度下单轴应变Si PMOS沟道反型层迁移率按晶面/晶向排序的理论模型.然而,在器件实际制造过程中,覆盖SiN应力膜工艺是固定的,由于沟道弹性劲度系数具有各向异性,这样,不同晶面/晶向应变PMOS沟道所受应力强度不同,进而导致在实际工艺下沟道反型层迁移率晶面/晶向排序理论模型"失效".针对该问题,本文采用中国科学院微电子研究所40 nm工艺流程制备了不同晶面/晶向40 nm沟道小尺寸单轴应变Si PMOS与未应变Si PMOS,并通过器件转移特性测试,获得了小尺寸单轴应变Si PMOS反型层迁移率晶面/晶向排序结论.此有关小尺寸单轴应变Si PMOS沟道反型层迁移率晶面/晶向排序的相关结论,由于考虑了工艺实现因素,与文献理论预测排序结果相比,更适于指导实际器件制造;相关分析方法也可为其他应变材料沟道MOS相关问题的解决提供重要技术参考.     

非对称Halo异质栅应变Si SOI MOSFET的二维解析模型

为了进一步提高深亚微米SOI (Silicon-On-Insulator) MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) 的电流驱动能力, 抑制短沟道效应和漏致势垒降低效应, 提出了非对称Halo异质栅应变Si SOI MOSFET. 在沟道源端一侧引入高掺杂Halo结构, 栅极由不同功函数的两种材料组成. 考虑新器件结构特点和应变的影响, 修正了平带电压和内建电势. 为新结构器件建立了全耗尽条件下的表面势和阈值电压二维解析模型. 模型详细分析了应变对表面势、表面场强、阈值电压的影响, 考虑了金属栅长度及功函数差变化的影响. 研究结果表明,提出的新器件结构能进一步提高电流驱动能力, 抑制短沟道效应和抑制漏致势垒降低效应, 为新器件物理参数设计提供了重要参考. 关键词： 非对称Halo 异质栅 应变Si 短沟道效应     

应变SiGe SOI量子阱沟道PMOSFET阈值电压模型研究

在绝缘层附着硅(SOI)结构的Si膜上生长SiGe合金制作具有SiGe量子阱沟道的SOI p型金属氧化物半导体场效应晶体管(PMOSFET)，该器件不仅具有SOI结构的优点，而且因量子阱中载流子迁移率高，所以进一步提高了器件的性能.在分析常规的Si SOI MOSFET基础上，建立了应变SiGe SOI 量子阱沟道PMOSFET的阈值电压模型和电流-电压(I-V)特性模型，利用Matlab对该结构器件的I-V特性、跨导及漏导特性进行了模拟分析，且与常规结构的器件作了对比.模拟结果表明，应变SiGe SOI量子阱沟道PMOSFET的性能均比常规结构的器件有大幅度提高. 关键词： 应变SiGe SOI MOSFET 阈值电压 模型     

单轴应变硅N沟道金属氧化物半导体场效应晶体管电容特性模型

电容特性模型是单轴应变硅金属氧化物半导体场效应晶体管(Si MOSFET)和电路进行瞬态分析、交流小信号分析、噪声分析等的重要基础. 本文首先建立了单轴应变Si NMOSFET 的16 个微分电容模型, 并将微分电容的仿真结果与实验结果进行了比较, 验证了所建模型的正确性. 同时对其中的关键性栅电容C_gg 与应力强度、偏置电压、沟道长度、栅极掺杂浓度等的关系进行了分析研究. 结果表明, 与体硅器件相比, 应变的引入使得单轴应变Si NMOSFET器件的栅电容增大, 随偏置电压、沟道长度、栅极掺杂浓度的变化趋势保持不变.     

堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管二维模型

提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.     

Significant improvement of OLED efficiency and stability by doping both HTL and ETL with different dopant in heterojunction of polymer/small-molecules

This paper reports that the polymer/organic heterojunction doped light-emitting diodes using a novel poly-TPD as hole transport material and doping both hole transport layer and emitter layer with the highly fluorescent rubrene and DCJTB has been successfully fabricated. The basic structure of the heterostructure is PTPD/Alq₃. When hole transport layer and electron transport layer are doped simultaneously with different dopant, the electroluminescence quantum efficiencies are about 3 times greater than that of the undoped device. Compared with undoped device and conventional TPD/Alq₃ diode, the stability of the doping device is significantly improved. The process of emission for doped device may include carrier trapping as well as F\"{o}rster energy transfer.     

含有δ掺杂层的SiGe pMOS量子阱沟道空穴面密度研究

建立了含有δ掺杂层的SiGe pMOS器件量子阱沟道中空穴面密度的静态与准静态物理模型，并对该模型进行了数值分析.讨论了静态时器件量子阱空穴面密度与δ掺杂层杂质浓度和本征层厚度的关系，阈值电压VT与δ掺杂层杂质浓度NA、量子阱沟道载流子面密度Ps及本征层厚度di等参数间的关系.同时还讨论了准静态时量子阱空穴面密度P′s与栅压VGS的关系. 关键词： δ掺杂层 空穴面密度     

单轴应变Si NMOSFET热载流子栅电流模型

热载流子效应产生的栅电流是影响器件功耗及可靠性的重要因素之一,本文基于热载流子形成的物理过程,建立了单轴应变硅NMOSFET热载流子栅电流模型,并对热载流子栅电流与应力强度、沟道掺杂浓度、栅源电压、漏源电压等的关系,以及TDDB(经时击穿)寿命与栅源电压的关系进行了分析研究.结果表明,与体硅器件相比,单轴应变硅MOS器件不仅具有较小的热载流子栅电流,而且可靠性也获得提高.同时模型仿真结果与单轴应变硅NMOSFET的实验结果符合较好,验证了该模型的可行性.     

Charge transfer modification of inverted planar perovskite solar cells by NiOx/Sr:NiOx bilayer hole transport layer

Perovskite solar cells (PSCs) are the most promising commercial photoelectric conversion technology in the future. The planar p-i-n structure cells have advantages in negligible hysteresis, low temperature preparation and excellent stability. However, for inverted planar PSCs, the non-radiative recombination at the interface is an important reason that impedes the charge transfer and improvement of power conversion efficiency. Having a homogeneous, compact, and energy-level-matched charge transport layer is the key to reducing non-radiative recombination. In our study, NiO$_{x}$/Sr:NiO$_{x}$ bilayer hole transport layer (HTL) improves the holes transmission of NiO$_{x}$ based HTL, reduces the recombination in the interface between perovskite and HTL layer and improves the device performance. The bilayer HTL enhances the hole transfer by forming a driving force of an electric field and further improves $J_{\rm sc}$. As a result, the device has a power conversion efficiency of 18.44%, a short circuit current density of 22.81 mA$\cdot$cm$^{-2}$ and a fill factor of 0.80. Compared to the pristine PSCs, there are certain improvements of optical parameters. This method provides a new idea for the future design of novel hole transport layers and the development of high-performance solar cells.     

Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson’s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.     

The study on two-dimensional analytical model for gate stack fully depleted strained Si on silicon-germanium-on-insulator MOSFETs

Based on the exact resultant solution of two-dimensional Poisson's equation in strained Si and Si_{1 - X}Ge_X layer, a simple and accurate two-dimensional analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator (SGOI) MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects (SCE), the drain-induced barrier-lowering (DIBL) and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.     

单轴应变Si(001)任意晶向电子电导有效质量模型

单轴应变Si材料电子电导有效质量是理解其电子迁移率增强的关键因素之一, 对其深入研究具有重要的理论意义和实用价值. 本文从Schrödinger方程出发, 将应力场考虑进来, 建立了单轴应变Si材料导带E-k解析模型. 并在此基础上, 最终建立了单轴应变Si(001)任意晶向电子电导率有效质量与应力强度和应力类型的关系模型. 本文的研究结果表明: 1) 单轴应力致电子迁移率增强的应力类型应选择张应力. 2) 单轴张应力情况下, 仅从电子电导有效质量角度考虑, [110]/(001)晶向与[100]/(001)晶向均可. 但考虑到态密度有效质量的因素, 应选择[110]/(001)晶向. 3) 沿(001)晶面上[110]晶向施加单轴张应力时, 若想进一步提高电子迁移率, 应选取[100]晶向为器件沟道方向. 以上结论可为应变Si nMOS器件性能增强的研究及导电沟道的应力与晶向设计提供重要理论依据. 关键词： 单轴应变 E-k关系')" href="#">E-k关系 电导有效质量     

Ge组分对应变Si1-xGe x 沟道p-MOSFET电学特性影响

利用二维数值模拟方法,研究了不同Ge组分应变Si_1-xGe _x 沟道p-MOSFET的电容-电压特性以及阈值电压的变化情况.计算结果表明:提高应变Si_1-xGe _x 沟道层中的Ge组分,器件亚阈值电流明显增大;栅电容在器件进入反型状态时产生显著变化;阈值电压的改变量与Ge组分基本成线性关系.通过改变Si_1-xGe _x 沟道的长度,并结 关键词： 1-xGe _x 沟道')" href="#">应变Si_1-xGe _x 沟道 p-MOSFET 空穴迁移率 栅电容     

n-type ZnS used as electron transport material in organic light-emitting diodes

This paper reports on the n-type ZnS used as electron transport layer for the organic light-emitting diodes (OLEDs). The naphthyl-substituted benzidine derivative (NPB) and tris (8-hydroxyquinoline) aluminium (AlqOLEDs n型ZnS 电子运输层 亮度 效率 功能发光二极管OLEDs, n-type ZnS, electron transport layer, luminance, efficiencyProject supported by the National Natural Science Foundation of China (Grant No 60476005), the Scientific Research Foundation for Returned Overseas Chinese Scholars, the State Education Ministry, the State Key Program for Basic Research of the Ministry of Science and Technology of China (Grant No 2003CB314707), and the Key Project of National Natural Science Foundation of China (Grant No 50532090).2005-11-211/9/2006 12:00:00 AMThis paper reports on the n-type ZnS used as electron transport layer for the organic light-emitting diodes （OLEDs）. The naphthyl-substituted benzidine derivative （NPB） and tris （8-hydroxyquinoline） aluminium （Alq3） are used as the hole transport layer and the emitting layer respectively. The insertion of the n-type ZnS layer enhances the electron injection in the OLEDs. The study was carried out on OLEDs of structures： indium-tin-oxide （ITO）/NPB/Alq3/ZnS/LiF/AL, ITO/NPB/Alq3/LiF/AL and ITO/NPB/Alq3/AL. The luminance and efficiency of the device containing this electron transport layer are increased significantly over those obtained from conventional devices due to better carrier balance.     

An analytical threshold voltage model for dual-strained channel PMOSFET

Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si 1-x Ge x /relaxd Si 1-y Ge y (s-Si/s-SiGe/Si 1-y Ge y) metal-oxide-semiconductor field-effect transistor (PMOSFET),an-alytical expressions of the threshold voltages for buried channel and surface channel are presented.And the maximum allowed thickness of s-Si is given,which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si),because the hole mobility in the buried channel is higher than that in the surface channel.Thus they offer a good accuracy as compared with the results of device simulator ISE.With this model,the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted,such as Ge fraction,layer thickness,and doping concentration.This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si 1-y Ge y metal-oxide-semiconductor field-effect transistor (MOSFET) designs.     

Study on a novel vertical enhancement-mode Ga2O3 MOSFET with FINFET structure

A novel enhanced mode(E-mode)Ga₂O₃ metal-oxide-semiconductor field-effect transistor(MOSFET)with vertical FINFET structure is proposed and the characteristics of that device are numerically investigated.It is found that the concentration of the source region and the width coupled with the height of the channel mainly effect the on-state characteristics.The metal material of the gate,the oxide material,the oxide thickness,and the epitaxial layer concentration strongly affect the threshold voltage and the output currents.Enabling an E-mode MOSFET device requires a large work function gate metal and an oxide with large dielectric constant.When the output current density of the device increases,the source concentration,the thickness of the epitaxial layer,and the total width of the device need to be expanded.The threshold voltage decreases with the increase of the width of the channel area under the same gate voltage.It is indicated that a set of optimal parameters of a practical vertical enhancement-mode Ga₂O₃ MOSFET requires the epitaxial layer concentration,the channel height of the device,the thickness of the source region,and the oxide thickness of the device should be less than 5×10¹⁶ cm^-3,less than 1.5μm,between 0.1μm-0.3μm and less than 0.08μm,respectively.     

A high rectification efficiency Si0.14Ge0.72Sn0.14–Ge0.82Sn0.18–Ge quantum structure n-MOSFET for 2.45 GHz weak energy microwave wireless energy transmission

The design strategy and efficiency optimization of a Ge-based n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET) with a Si_0.14Ge_0.72Sn_0.14-Ge_0.82Sn_0.18-Ge quantum structure used for 2.45 GHz weak energy microwave wireless energy transmission is reported. The quantum structure combined with δ-doping technology is used to reduce the scattering of the device and improve its electron mobility; at the same time, the generation of surface channels is suppressed by the Si_0.14Ge_0.72Sn_0.14 cap layer. By adjusting the threshold voltage of the device to 91 mV, setting the device aspect ratio to 1 μm/0.4 μm and adopting a novel diode connection method, the rectification efficiency of the device is improved. With simulation by Silvaco TCAD software, good performance is displayed in the transfer and output characteristics. For a simple half-wave rectifier circuit with a load of 1 pf and 20 kΩ , the rectification efficiency of the device can reach 7.14% at an input power of -10 dBm, which is 4.2 times that of a Si MOSFET (with a threshold voltage of 80 mV) under the same conditions; this device shows a better rectification effect than a Si MOSFET in the range of -30 dBm to 6.9 dBm.